Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T62,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T62,T33,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T62,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T62,T33
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T62,T33,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T62,T33,T36
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14335077	14933	0	0
gen_assertions[0].RstEnOn_A	14335077	1148	0	0
gen_assertions[0].RstNOff_A	14335077	14933	0	0
gen_assertions[0].RstNOn_A	14335077	1148	0	0
gen_assertions[1].RstEnOff_A	57339003	13562	0	0
gen_assertions[1].RstEnOn_A	57339003	1128	0	0
gen_assertions[1].RstNOff_A	57339003	13562	0	0
gen_assertions[1].RstNOn_A	57339003	1128	0	0
gen_assertions[2].RstEnOff_A	28670712	13629	0	0
gen_assertions[2].RstEnOn_A	28670712	1134	0	0
gen_assertions[2].RstNOff_A	28670712	13629	0	0
gen_assertions[2].RstNOn_A	28670712	1134	0	0
gen_assertions[3].RstEnOff_A	28670751	13675	0	0
gen_assertions[3].RstEnOn_A	28670751	1159	0	0
gen_assertions[3].RstNOff_A	28670751	13675	0	0
gen_assertions[3].RstNOn_A	28670751	1159	0	0
gen_assertions[4].RstEnOff_A	1809921	23191	0	0
gen_assertions[4].RstEnOn_A	1809921	1202	0	0
gen_assertions[4].RstNOff_A	1809921	23191	0	0
gen_assertions[4].RstNOn_A	1809921	1202	0	0
gen_assertions[5].RstEnOff_A	14335077	15232	0	0
gen_assertions[5].RstEnOn_A	14335077	1290	0	0
gen_assertions[5].RstNOff_A	14335077	15232	0	0
gen_assertions[5].RstNOn_A	14335077	1290	0	0
gen_assertions[6].RstEnOff_A	14335077	15261	0	0
gen_assertions[6].RstEnOn_A	14335077	1316	0	0
gen_assertions[6].RstNOff_A	14335077	15261	0	0
gen_assertions[6].RstNOn_A	14335077	1316	0	0
gen_assertions[7].RstEnOff_A	14335077	15310	0	0
gen_assertions[7].RstEnOn_A	14335077	1370	0	0
gen_assertions[7].RstNOff_A	14335077	15310	0	0
gen_assertions[7].RstNOn_A	14335077	1370	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	14933	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	4	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	3	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1148	0	0
T2	4810	1	0	0
T3	2339	0	0	0
T4	4349	0	0	0
T5	4098	6	0	0
T6	4027	6	0	0
T7	5143	0	0	0
T8	2948	0	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T11	2288	0	0	0
T12	0	4	0	0
T33	0	3	0	0
T36	0	38	0	0
T62	0	3	0	0
T63	0	5	0	0
T70	0	1	0	0
T92	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	14933	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	4	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	3	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1148	0	0
T2	4810	1	0	0
T3	2339	0	0	0
T4	4349	0	0	0
T5	4098	6	0	0
T6	4027	6	0	0
T7	5143	0	0	0
T8	2948	0	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T11	2288	0	0	0
T12	0	4	0	0
T33	0	3	0	0
T36	0	38	0	0
T62	0	3	0	0
T63	0	5	0	0
T70	0	1	0	0
T92	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57339003	13562	0	0
T1	12984	3	0	0
T2	19240	15	0	0
T3	9358	0	0	0
T4	17400	4	0	0
T5	16392	20	0	0
T6	16111	17	0	0
T7	20575	0	0	0
T8	11793	4	0	0
T9	23394	0	0	0
T10	23320	0	0	0
T12	0	16	0	0
T20	0	24	0	0
T21	0	33	0	0
T62	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57339003	1128	0	0
T2	19240	1	0	0
T3	9358	0	0	0
T4	17400	0	0	0
T5	16392	5	0	0
T6	16111	3	0	0
T7	20575	0	0	0
T8	11793	1	0	0
T9	23394	0	0	0
T10	23320	0	0	0
T11	9159	0	0	0
T33	0	1	0	0
T36	0	41	0	0
T62	0	4	0	0
T63	0	5	0	0
T92	0	3	0	0
T93	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57339003	13562	0	0
T1	12984	3	0	0
T2	19240	15	0	0
T3	9358	0	0	0
T4	17400	4	0	0
T5	16392	20	0	0
T6	16111	17	0	0
T7	20575	0	0	0
T8	11793	4	0	0
T9	23394	0	0	0
T10	23320	0	0	0
T12	0	16	0	0
T20	0	24	0	0
T21	0	33	0	0
T62	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57339003	1128	0	0
T2	19240	1	0	0
T3	9358	0	0	0
T4	17400	0	0	0
T5	16392	5	0	0
T6	16111	3	0	0
T7	20575	0	0	0
T8	11793	1	0	0
T9	23394	0	0	0
T10	23320	0	0	0
T11	9159	0	0	0
T33	0	1	0	0
T36	0	41	0	0
T62	0	4	0	0
T63	0	5	0	0
T92	0	3	0	0
T93	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670712	13629	0	0
T1	6490	3	0	0
T2	9619	15	0	0
T3	4679	0	0	0
T4	8699	4	0	0
T5	8196	20	0	0
T6	8056	17	0	0
T7	10288	0	0	0
T8	5895	4	0	0
T9	11694	0	0	0
T10	11660	0	0	0
T12	0	16	0	0
T20	0	24	0	0
T21	0	33	0	0
T62	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670712	1134	0	0
T8	5895	1	0	0
T9	11694	0	0	0
T10	11660	0	0	0
T11	4579	0	0	0
T12	11205	0	0	0
T20	48340	0	0	0
T21	27255	0	0	0
T22	12231	1	0	0
T33	0	4	0	0
T36	0	41	0	0
T62	6053	4	0	0
T63	0	7	0	0
T74	11654	0	0	0
T92	0	6	0	0
T93	0	5	0	0
T94	0	7	0	0
T95	0	2	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670712	13629	0	0
T1	6490	3	0	0
T2	9619	15	0	0
T3	4679	0	0	0
T4	8699	4	0	0
T5	8196	20	0	0
T6	8056	17	0	0
T7	10288	0	0	0
T8	5895	4	0	0
T9	11694	0	0	0
T10	11660	0	0	0
T12	0	16	0	0
T20	0	24	0	0
T21	0	33	0	0
T62	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670712	1134	0	0
T8	5895	1	0	0
T9	11694	0	0	0
T10	11660	0	0	0
T11	4579	0	0	0
T12	11205	0	0	0
T20	48340	0	0	0
T21	27255	0	0	0
T22	12231	1	0	0
T33	0	4	0	0
T36	0	41	0	0
T62	6053	4	0	0
T63	0	7	0	0
T74	11654	0	0	0
T92	0	6	0	0
T93	0	5	0	0
T94	0	7	0	0
T95	0	2	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670751	13675	0	0
T1	6492	3	0	0
T2	9619	15	0	0
T3	4680	0	0	0
T4	8697	4	0	0
T5	8196	20	0	0
T6	8056	17	0	0
T7	10288	0	0	0
T8	5894	3	0	0
T9	11703	0	0	0
T10	11656	0	0	0
T12	0	16	0	0
T20	0	24	0	0
T21	0	33	0	0
T62	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670751	1159	0	0
T13	7994	0	0	0
T21	27266	0	0	0
T22	12235	0	0	0
T33	0	5	0	0
T36	0	38	0	0
T51	2926	0	0	0
T62	6053	5	0	0
T63	0	8	0	0
T78	3245	0	0	0
T79	3926	0	0	0
T90	52446	0	0	0
T91	8382	0	0	0
T92	0	6	0	0
T93	0	5	0	0
T94	0	6	0	0
T95	0	4	0	0
T96	0	6	0	0
T97	0	14	0	0
T98	11724	0	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670751	13675	0	0
T1	6492	3	0	0
T2	9619	15	0	0
T3	4680	0	0	0
T4	8697	4	0	0
T5	8196	20	0	0
T6	8056	17	0	0
T7	10288	0	0	0
T8	5894	3	0	0
T9	11703	0	0	0
T10	11656	0	0	0
T12	0	16	0	0
T20	0	24	0	0
T21	0	33	0	0
T62	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670751	1159	0	0
T13	7994	0	0	0
T21	27266	0	0	0
T22	12235	0	0	0
T33	0	5	0	0
T36	0	38	0	0
T51	2926	0	0	0
T62	6053	5	0	0
T63	0	8	0	0
T78	3245	0	0	0
T79	3926	0	0	0
T90	52446	0	0	0
T91	8382	0	0	0
T92	0	6	0	0
T93	0	5	0	0
T94	0	6	0	0
T95	0	4	0	0
T96	0	6	0	0
T97	0	14	0	0
T98	11724	0	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	23191	0	0
T1	404	6	0	0
T2	599	16	0	0
T3	290	2	0	0
T4	542	6	0	0
T5	510	21	0	0
T6	502	19	0	0
T7	641	2	0	0
T8	368	6	0	0
T9	733	3	0	0
T10	731	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	1202	0	0
T8	368	1	0	0
T9	733	0	0	0
T10	731	0	0	0
T11	286	0	0	0
T12	699	0	0	0
T20	3043	0	0	0
T21	1791	0	0	0
T22	763	1	0	0
T33	0	6	0	0
T36	0	37	0	0
T62	376	8	0	0
T63	0	9	0	0
T70	0	1	0	0
T74	731	0	0	0
T92	0	7	0	0
T93	0	6	0	0
T94	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	23191	0	0
T1	404	6	0	0
T2	599	16	0	0
T3	290	2	0	0
T4	542	6	0	0
T5	510	21	0	0
T6	502	19	0	0
T7	641	2	0	0
T8	368	6	0	0
T9	733	3	0	0
T10	731	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	1202	0	0
T8	368	1	0	0
T9	733	0	0	0
T10	731	0	0	0
T11	286	0	0	0
T12	699	0	0	0
T20	3043	0	0	0
T21	1791	0	0	0
T22	763	1	0	0
T33	0	6	0	0
T36	0	37	0	0
T62	376	8	0	0
T63	0	9	0	0
T70	0	1	0	0
T74	731	0	0	0
T92	0	7	0	0
T93	0	6	0	0
T94	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	15232	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	5	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1290	0	0
T8	2948	1	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T11	2288	0	0	0
T12	5601	0	0	0
T20	24171	0	0	0
T21	13629	0	0	0
T22	6115	0	0	0
T33	0	7	0	0
T36	0	39	0	0
T62	3025	9	0	0
T63	0	10	0	0
T74	5828	0	0	0
T92	0	8	0	0
T93	0	7	0	0
T94	0	11	0	0
T95	0	5	0	0
T96	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	15232	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	5	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1290	0	0
T8	2948	1	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T11	2288	0	0	0
T12	5601	0	0	0
T20	24171	0	0	0
T21	13629	0	0	0
T22	6115	0	0	0
T33	0	7	0	0
T36	0	39	0	0
T62	3025	9	0	0
T63	0	10	0	0
T74	5828	0	0	0
T92	0	8	0	0
T93	0	7	0	0
T94	0	11	0	0
T95	0	5	0	0
T96	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	15261	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	4	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	9	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1316	0	0
T13	3997	0	0	0
T21	13629	0	0	0
T22	6115	0	0	0
T33	0	8	0	0
T36	0	34	0	0
T51	1462	0	0	0
T62	3025	9	0	0
T63	0	11	0	0
T78	1622	0	0	0
T79	1963	0	0	0
T90	26227	0	0	0
T91	4190	0	0	0
T92	0	9	0	0
T93	0	9	0	0
T94	0	11	0	0
T95	0	7	0	0
T96	0	7	0	0
T97	0	13	0	0
T98	5861	0	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	15261	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	4	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	9	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1316	0	0
T13	3997	0	0	0
T21	13629	0	0	0
T22	6115	0	0	0
T33	0	8	0	0
T36	0	34	0	0
T51	1462	0	0	0
T62	3025	9	0	0
T63	0	11	0	0
T78	1622	0	0	0
T79	1963	0	0	0
T90	26227	0	0	0
T91	4190	0	0	0
T92	0	9	0	0
T93	0	9	0	0
T94	0	11	0	0
T95	0	7	0	0
T96	0	7	0	0
T97	0	13	0	0
T98	5861	0	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	15310	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	4	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	11	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1370	0	0
T13	3997	0	0	0
T21	13629	0	0	0
T22	6115	0	0	0
T33	0	9	0	0
T36	0	44	0	0
T51	1462	0	0	0
T62	3025	11	0	0
T63	0	10	0	0
T78	1622	0	0	0
T79	1963	0	0	0
T90	26227	0	0	0
T91	4190	0	0	0
T92	0	10	0	0
T93	0	10	0	0
T94	0	14	0	0
T95	0	8	0	0
T96	0	6	0	0
T97	0	13	0	0
T98	5861	0	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	15310	0	0
T1	3245	4	0	0
T2	4810	15	0	0
T3	2339	0	0	0
T4	4349	4	0	0
T5	4098	20	0	0
T6	4027	19	0	0
T7	5143	0	0	0
T8	2948	4	0	0
T9	5849	0	0	0
T10	5831	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T62	0	11	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	1370	0	0
T13	3997	0	0	0
T21	13629	0	0	0
T22	6115	0	0	0
T33	0	9	0	0
T36	0	44	0	0
T51	1462	0	0	0
T62	3025	11	0	0
T63	0	10	0	0
T78	1622	0	0	0
T79	1963	0	0	0
T90	26227	0	0	0
T91	4190	0	0	0
T92	0	10	0	0
T93	0	10	0	0
T94	0	14	0	0
T95	0	8	0	0
T96	0	6	0	0
T97	0	13	0	0
T98	5861	0	0	0