Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13492720	7823	0	0
alert_regwen_rd_A	13492720	7433	0	0
cpu_regwen_rd_A	13492720	7531	0	0
sw_rst_ctrl_n_0_rd_A	13492720	14035	0	0
sw_rst_ctrl_n_1_rd_A	13492720	13846	0	0
sw_rst_ctrl_n_2_rd_A	13492720	14199	0	0
sw_rst_ctrl_n_3_rd_A	13492720	13905	0	0
sw_rst_ctrl_n_4_rd_A	13492720	14239	0	0
sw_rst_ctrl_n_5_rd_A	13492720	13862	0	0
sw_rst_ctrl_n_6_rd_A	13492720	13857	0	0
sw_rst_ctrl_n_7_rd_A	13492720	14192	0	0
sw_rst_regwen_0_rd_A	13492720	7823	0	0
sw_rst_regwen_1_rd_A	13492720	7896	0	0
sw_rst_regwen_2_rd_A	13492720	7986	0	0
sw_rst_regwen_3_rd_A	13492720	7913	0	0
sw_rst_regwen_4_rd_A	13492720	7716	0	0
sw_rst_regwen_5_rd_A	13492720	8072	0	0
sw_rst_regwen_6_rd_A	13492720	8155	0	0
sw_rst_regwen_7_rd_A	13492720	7982	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7823	0	0
T65	2755	66	0	0
T67	9147	1	0	0
T68	3919	117	0	0
T71	3194	268	0	0
T72	21544	3	0	0
T73	11686	356	0	0
T100	10793	2	0	0
T101	8819	421	0	0
T102	4577	126	0	0
T103	4808	677	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7433	0	0
T14	4580	0	0	0
T15	5351	0	0	0
T36	244738	413	0	0
T37	5658	0	0	0
T38	36061	43	0	0
T39	4108	0	0	0
T52	5493	0	0	0
T70	5227	0	0	0
T84	0	144	0	0
T97	0	30	0	0
T107	16799	0	0	0
T108	0	78	0	0
T109	0	56	0	0
T112	0	284	0	0
T113	0	614	0	0
T114	0	57	0	0
T128	0	441	0	0
T129	2162	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7531	0	0
T14	4580	0	0	0
T15	5351	0	0	0
T36	244738	406	0	0
T37	5658	0	0	0
T38	36061	68	0	0
T39	4108	0	0	0
T52	5493	0	0	0
T70	5227	0	0	0
T84	0	158	0	0
T97	0	47	0	0
T107	16799	0	0	0
T108	0	73	0	0
T109	0	66	0	0
T112	0	296	0	0
T113	0	682	0	0
T114	0	38	0	0
T128	0	503	0	0
T129	2162	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	14035	0	0
T12	4460	42	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	21	0	0
T33	0	122	0	0
T36	0	973	0	0
T38	0	79	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	7	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	165	0	0
T97	0	199	0	0
T108	0	72	0	0
T109	0	76	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	13846	0	0
T12	4460	45	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	18	0	0
T33	0	123	0	0
T36	0	930	0	0
T38	0	89	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	14	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	158	0	0
T97	0	226	0	0
T108	0	81	0	0
T109	0	71	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	14199	0	0
T12	4460	50	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	14	0	0
T33	0	113	0	0
T36	0	992	0	0
T38	0	62	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	11	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	241	0	0
T97	0	219	0	0
T108	0	104	0	0
T109	0	66	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	13905	0	0
T12	4460	51	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	24	0	0
T33	0	127	0	0
T36	0	1039	0	0
T38	0	50	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	9	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	173	0	0
T97	0	193	0	0
T108	0	71	0	0
T109	0	65	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	14239	0	0
T12	4460	62	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	18	0	0
T33	0	156	0	0
T36	0	938	0	0
T38	0	63	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	20	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	188	0	0
T97	0	234	0	0
T108	0	76	0	0
T109	0	58	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	13862	0	0
T12	4460	23	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	20	0	0
T33	0	178	0	0
T36	0	929	0	0
T38	0	74	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	14	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	173	0	0
T97	0	192	0	0
T108	0	77	0	0
T109	0	53	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	13857	0	0
T12	4460	26	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	6	0	0
T33	0	136	0	0
T36	0	858	0	0
T38	0	62	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T70	0	4	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	171	0	0
T97	0	225	0	0
T108	0	67	0	0
T109	0	60	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	14192	0	0
T12	4460	44	0	0
T13	3930	0	0	0
T20	18869	0	0	0
T21	10049	0	0	0
T22	5875	15	0	0
T33	0	156	0	0
T36	0	948	0	0
T38	0	73	0	0
T47	0	14	0	0
T51	1444	0	0	0
T62	3007	0	0	0
T74	5476	0	0	0
T78	1531	0	0	0
T91	4043	0	0	0
T94	0	184	0	0
T97	0	194	0	0
T108	0	60	0	0
T109	0	55	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7823	0	0
T13	3930	0	0	0
T22	5875	4	0	0
T23	26206	0	0	0
T33	9574	31	0	0
T36	0	439	0	0
T38	0	67	0	0
T47	0	10	0	0
T51	1444	0	0	0
T70	0	3	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	27	0	0
T97	0	34	0	0
T98	5699	0	0	0
T108	0	70	0	0
T109	0	52	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7896	0	0
T13	3930	0	0	0
T22	5875	3	0	0
T23	26206	0	0	0
T33	9574	28	0	0
T36	0	416	0	0
T38	0	61	0	0
T47	0	3	0	0
T51	1444	0	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	11	0	0
T97	0	45	0	0
T98	5699	0	0	0
T108	0	74	0	0
T109	0	65	0	0
T112	0	312	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7986	0	0
T13	3930	0	0	0
T22	5875	1	0	0
T23	26206	0	0	0
T33	9574	29	0	0
T36	0	434	0	0
T38	0	74	0	0
T47	0	4	0	0
T51	1444	0	0	0
T70	0	1	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	28	0	0
T97	0	43	0	0
T98	5699	0	0	0
T108	0	75	0	0
T109	0	52	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7913	0	0
T13	3930	0	0	0
T22	5875	12	0	0
T23	26206	0	0	0
T33	9574	24	0	0
T36	0	396	0	0
T38	0	76	0	0
T47	0	8	0	0
T51	1444	0	0	0
T70	0	7	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	32	0	0
T97	0	25	0	0
T98	5699	0	0	0
T108	0	81	0	0
T109	0	62	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7716	0	0
T13	3930	0	0	0
T22	5875	5	0	0
T23	26206	0	0	0
T33	9574	33	0	0
T36	0	361	0	0
T38	0	63	0	0
T47	0	14	0	0
T51	1444	0	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	24	0	0
T97	0	47	0	0
T98	5699	0	0	0
T108	0	77	0	0
T109	0	59	0	0
T112	0	330	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	8072	0	0
T13	3930	0	0	0
T22	5875	7	0	0
T23	26206	0	0	0
T33	9574	26	0	0
T36	0	444	0	0
T38	0	66	0	0
T47	0	15	0	0
T51	1444	0	0	0
T70	0	1	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	41	0	0
T97	0	36	0	0
T98	5699	0	0	0
T108	0	67	0	0
T109	0	59	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	8155	0	0
T13	3930	0	0	0
T22	5875	6	0	0
T23	26206	0	0	0
T33	9574	29	0	0
T36	0	479	0	0
T38	0	48	0	0
T47	0	13	0	0
T51	1444	0	0	0
T70	0	7	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	38	0	0
T97	0	31	0	0
T98	5699	0	0	0
T108	0	77	0	0
T109	0	70	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13492720	7982	0	0
T13	3930	0	0	0
T22	5875	8	0	0
T23	26206	0	0	0
T33	9574	35	0	0
T36	0	392	0	0
T38	0	55	0	0
T47	0	12	0	0
T51	1444	0	0	0
T70	0	1	0	0
T78	1531	0	0	0
T79	1872	0	0	0
T90	20161	0	0	0
T91	4043	0	0	0
T94	0	31	0	0
T97	0	47	0	0
T98	5699	0	0	0
T108	0	83	0	0
T109	0	52	0	0