Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7833

1

T1

17

T2

33

T8

166

auto[1]

10763

1

T1

84

T2

23

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5761	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6269	1			T1	27		T2	18		T3	1
reset_info_cp[2]	2910	1			T1	16		T2	13		T4	1
reset_info_cp[4]	3731	1			T1	18		T2	12		T4	1
reset_info_cp[8]	105	1			T8	2		T12	5		T24	1
reset_info_cp[16]	113	1			T1	2		T8	1		T12	1
reset_info_cp[32]	103	1			T2	1		T5	1		T12	1
reset_info_cp[64]	107	1			T1	1		T8	1		T24	1
reset_info_cp[128]	117	1			T8	1		T10	1		T12	6

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3066	1			T1	17		T2	12		T8	61
reset_info_cp[1]	auto[1]	2583	1			T1	9		T2	5		T4	1
reset_info_cp[2]	auto[0]	859	1			T2	6		T8	19		T10	5
reset_info_cp[2]	auto[1]	2051	1			T1	16		T2	7		T4	1
reset_info_cp[4]	auto[0]	1300	1			T2	8		T8	36		T10	8
reset_info_cp[4]	auto[1]	2431	1			T1	18		T2	4		T4	1
reset_info_cp[8]	auto[0]	43	1			T8	1		T12	2		T25	1
reset_info_cp[8]	auto[1]	62	1			T8	1		T12	3		T24	1
reset_info_cp[16]	auto[0]	48	1			T24	2		T27	1		T102	1
reset_info_cp[16]	auto[1]	65	1			T1	2		T8	1		T12	1
reset_info_cp[32]	auto[0]	41	1			T2	1		T132	1		T51	1
reset_info_cp[32]	auto[1]	62	1			T5	1		T12	1		T25	1
reset_info_cp[64]	auto[0]	44	1			T8	1		T94	1		T38	1
reset_info_cp[64]	auto[1]	63	1			T1	1		T24	1		T53	1
reset_info_cp[128]	auto[0]	41	1			T8	1		T12	2		T102	1
reset_info_cp[128]	auto[1]	76	1			T10	1		T12	4		T45	2