Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3210560659 Jul 29 05:02:07 PM PDT 24 Jul 29 05:02:08 PM PDT 24 245289189 ps
T539 /workspace/coverage/default/31.rstmgr_por_stretcher.3047668964 Jul 29 05:02:14 PM PDT 24 Jul 29 05:02:15 PM PDT 24 210155835 ps
T540 /workspace/coverage/default/35.rstmgr_alert_test.3781720954 Jul 29 05:02:36 PM PDT 24 Jul 29 05:02:37 PM PDT 24 61492406 ps
T541 /workspace/coverage/default/2.rstmgr_alert_test.2874129872 Jul 29 05:00:10 PM PDT 24 Jul 29 05:00:11 PM PDT 24 90238519 ps
T542 /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.817569650 Jul 29 05:02:26 PM PDT 24 Jul 29 05:02:34 PM PDT 24 1886251178 ps
T72 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.695617466 Jul 29 04:55:10 PM PDT 24 Jul 29 04:55:11 PM PDT 24 142498278 ps
T73 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2339189263 Jul 29 04:55:09 PM PDT 24 Jul 29 04:55:11 PM PDT 24 271735189 ps
T68 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.942709047 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:25 PM PDT 24 1546464079 ps
T69 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3587614021 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:25 PM PDT 24 68120035 ps
T70 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3424671843 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:18 PM PDT 24 489664457 ps
T71 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.670052970 Jul 29 04:55:37 PM PDT 24 Jul 29 04:55:40 PM PDT 24 935921512 ps
T109 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2893594318 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:17 PM PDT 24 256246634 ps
T74 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1499535125 Jul 29 04:55:49 PM PDT 24 Jul 29 04:55:53 PM PDT 24 529318086 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1429178104 Jul 29 04:55:31 PM PDT 24 Jul 29 04:55:32 PM PDT 24 141818061 ps
T80 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.939244083 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:25 PM PDT 24 182106211 ps
T95 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3111136269 Jul 29 04:55:25 PM PDT 24 Jul 29 04:55:28 PM PDT 24 1156920711 ps
T96 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.331580995 Jul 29 04:55:49 PM PDT 24 Jul 29 04:55:50 PM PDT 24 126911490 ps
T97 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.804130871 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:24 PM PDT 24 903905917 ps
T110 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2340824362 Jul 29 04:55:40 PM PDT 24 Jul 29 04:55:42 PM PDT 24 222202817 ps
T111 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3890585629 Jul 29 04:55:34 PM PDT 24 Jul 29 04:55:35 PM PDT 24 138399351 ps
T112 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3960148059 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:25 PM PDT 24 64564606 ps
T119 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1649658223 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:30 PM PDT 24 785361841 ps
T98 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4041130569 Jul 29 04:55:39 PM PDT 24 Jul 29 04:55:41 PM PDT 24 317958965 ps
T99 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4277108741 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:16 PM PDT 24 208034705 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4245001211 Jul 29 04:55:28 PM PDT 24 Jul 29 04:55:32 PM PDT 24 267910179 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4225257414 Jul 29 04:55:30 PM PDT 24 Jul 29 04:55:39 PM PDT 24 1559926773 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.370169770 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:21 PM PDT 24 94446546 ps
T100 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1880744310 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:38 PM PDT 24 303453494 ps
T547 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3670594613 Jul 29 04:55:39 PM PDT 24 Jul 29 04:55:40 PM PDT 24 75074366 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1766012296 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:26 PM PDT 24 364699210 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.851892389 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:25 PM PDT 24 173946779 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2426323629 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:24 PM PDT 24 237659925 ps
T114 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3930298771 Jul 29 04:55:34 PM PDT 24 Jul 29 04:55:36 PM PDT 24 98778715 ps
T122 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4834501 Jul 29 04:55:28 PM PDT 24 Jul 29 04:55:30 PM PDT 24 504816855 ps
T549 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2672642233 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:16 PM PDT 24 184731575 ps
T550 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.753660898 Jul 29 04:55:09 PM PDT 24 Jul 29 04:55:10 PM PDT 24 91523783 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1398447841 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:09 PM PDT 24 123162155 ps
T115 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3111009929 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:24 PM PDT 24 97618365 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2048005711 Jul 29 04:55:28 PM PDT 24 Jul 29 04:55:31 PM PDT 24 789623955 ps
T127 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3605263914 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:22 PM PDT 24 532612265 ps
T124 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2470955699 Jul 29 04:55:31 PM PDT 24 Jul 29 04:55:35 PM PDT 24 557866917 ps
T552 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1506315776 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:15 PM PDT 24 505584476 ps
T134 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4134655260 Jul 29 04:55:49 PM PDT 24 Jul 29 04:55:52 PM PDT 24 522667023 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1098655395 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:23 PM PDT 24 360863844 ps
T116 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3799373741 Jul 29 04:55:01 PM PDT 24 Jul 29 04:55:02 PM PDT 24 58321824 ps
T135 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3649404972 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:37 PM PDT 24 425159627 ps
T117 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3259847978 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:21 PM PDT 24 54114177 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.290221706 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:01 PM PDT 24 69947353 ps
T118 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1936032266 Jul 29 04:55:13 PM PDT 24 Jul 29 04:55:14 PM PDT 24 74987580 ps
T555 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1615517771 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:16 PM PDT 24 187571995 ps
T125 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.589726042 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:29 PM PDT 24 217869544 ps
T121 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2946295689 Jul 29 04:55:38 PM PDT 24 Jul 29 04:55:39 PM PDT 24 424946937 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.891029336 Jul 29 04:55:37 PM PDT 24 Jul 29 04:55:38 PM PDT 24 128150297 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.234325362 Jul 29 04:55:46 PM PDT 24 Jul 29 04:55:47 PM PDT 24 142151068 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1557993954 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:01 PM PDT 24 115665538 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1135241417 Jul 29 04:55:51 PM PDT 24 Jul 29 04:55:52 PM PDT 24 105021812 ps
T560 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2377406155 Jul 29 04:55:52 PM PDT 24 Jul 29 04:55:53 PM PDT 24 132530322 ps
T561 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1778314786 Jul 29 04:55:49 PM PDT 24 Jul 29 04:55:50 PM PDT 24 71399351 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.594638150 Jul 29 04:55:31 PM PDT 24 Jul 29 04:55:37 PM PDT 24 1030203785 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2769768457 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:25 PM PDT 24 102397756 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1445334165 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:21 PM PDT 24 178957826 ps
T565 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1412406616 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:37 PM PDT 24 180039106 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.357715905 Jul 29 04:55:28 PM PDT 24 Jul 29 04:55:30 PM PDT 24 102871024 ps
T567 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.768002729 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:18 PM PDT 24 117081658 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3609955102 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:07 PM PDT 24 90456735 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1552902642 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:22 PM PDT 24 116790291 ps
T126 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1010775252 Jul 29 04:55:29 PM PDT 24 Jul 29 04:55:32 PM PDT 24 883670421 ps
T570 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3113007715 Jul 29 04:55:25 PM PDT 24 Jul 29 04:55:26 PM PDT 24 78608173 ps
T571 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3201872332 Jul 29 04:55:49 PM PDT 24 Jul 29 04:55:52 PM PDT 24 922546148 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.599384571 Jul 29 04:55:03 PM PDT 24 Jul 29 04:55:05 PM PDT 24 159404287 ps
T573 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3152612824 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:22 PM PDT 24 69896354 ps
T574 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3111858365 Jul 29 04:55:40 PM PDT 24 Jul 29 04:55:42 PM PDT 24 216237902 ps
T575 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3844309784 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:21 PM PDT 24 137780288 ps
T576 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2949152589 Jul 29 04:55:36 PM PDT 24 Jul 29 04:55:37 PM PDT 24 60568344 ps
T577 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.466549656 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:30 PM PDT 24 176446034 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1187030508 Jul 29 04:55:37 PM PDT 24 Jul 29 04:55:39 PM PDT 24 159910517 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1556577713 Jul 29 04:55:41 PM PDT 24 Jul 29 04:55:42 PM PDT 24 63699649 ps
T580 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2222207026 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:28 PM PDT 24 90411801 ps
T581 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.204968454 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:17 PM PDT 24 231913222 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3764561624 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:14 PM PDT 24 757985305 ps
T583 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2374478838 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:16 PM PDT 24 65374271 ps
T584 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2338548406 Jul 29 04:55:44 PM PDT 24 Jul 29 04:55:45 PM PDT 24 101911980 ps
T585 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2652517799 Jul 29 04:55:33 PM PDT 24 Jul 29 04:55:34 PM PDT 24 66239233 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3791843878 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:18 PM PDT 24 236705915 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1685476336 Jul 29 04:55:17 PM PDT 24 Jul 29 04:55:18 PM PDT 24 77124020 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.336813478 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:02 PM PDT 24 200488883 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3867560607 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:07 PM PDT 24 890958065 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2895310123 Jul 29 04:55:57 PM PDT 24 Jul 29 04:55:58 PM PDT 24 99989993 ps
T590 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.21655951 Jul 29 04:55:39 PM PDT 24 Jul 29 04:55:40 PM PDT 24 76481645 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2297807232 Jul 29 04:55:37 PM PDT 24 Jul 29 04:55:39 PM PDT 24 243620620 ps
T128 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2652116173 Jul 29 04:55:33 PM PDT 24 Jul 29 04:55:35 PM PDT 24 415196018 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.330868760 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:36 PM PDT 24 72241861 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3000585222 Jul 29 04:55:19 PM PDT 24 Jul 29 04:55:20 PM PDT 24 154649446 ps
T594 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3825351800 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:38 PM PDT 24 165779397 ps
T595 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2478909684 Jul 29 04:55:26 PM PDT 24 Jul 29 04:55:27 PM PDT 24 134456323 ps
T596 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2205254080 Jul 29 04:55:32 PM PDT 24 Jul 29 04:55:34 PM PDT 24 231827735 ps
T597 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1032491196 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:19 PM PDT 24 881079492 ps
T598 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2361486925 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:28 PM PDT 24 193283766 ps
T599 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2248839549 Jul 29 04:55:29 PM PDT 24 Jul 29 04:55:32 PM PDT 24 132744956 ps
T600 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2831245215 Jul 29 04:55:40 PM PDT 24 Jul 29 04:55:42 PM PDT 24 127313893 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2062903212 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:15 PM PDT 24 135200399 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1670345696 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:17 PM PDT 24 830863308 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1164885596 Jul 29 04:55:33 PM PDT 24 Jul 29 04:55:34 PM PDT 24 77203955 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2283177061 Jul 29 04:55:33 PM PDT 24 Jul 29 04:55:36 PM PDT 24 923711422 ps
T605 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2506642888 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:37 PM PDT 24 268902669 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.196625228 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:16 PM PDT 24 103159158 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3958171151 Jul 29 04:55:19 PM PDT 24 Jul 29 04:55:21 PM PDT 24 108915896 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1438308210 Jul 29 04:55:31 PM PDT 24 Jul 29 04:55:32 PM PDT 24 120146932 ps
T609 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3008045639 Jul 29 04:55:25 PM PDT 24 Jul 29 04:55:26 PM PDT 24 194941696 ps
T610 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2510877910 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:27 PM PDT 24 148994969 ps
T611 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3477731631 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:24 PM PDT 24 91862187 ps
T612 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.51564336 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:22 PM PDT 24 72741060 ps
T613 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.801876157 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:05 PM PDT 24 803583741 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1866212991 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:27 PM PDT 24 325864228 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4123484674 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:18 PM PDT 24 411573595 ps
T616 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3819355683 Jul 29 04:55:25 PM PDT 24 Jul 29 04:55:26 PM PDT 24 129775151 ps
T617 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2252280514 Jul 29 04:55:29 PM PDT 24 Jul 29 04:55:30 PM PDT 24 183826759 ps
T618 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.285310864 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:22 PM PDT 24 116774321 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2267068732 Jul 29 04:55:30 PM PDT 24 Jul 29 04:55:31 PM PDT 24 73613767 ps
T620 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1747056321 Jul 29 04:55:22 PM PDT 24 Jul 29 04:55:23 PM PDT 24 56900206 ps

Test location /workspace/coverage/default/23.rstmgr_stress_all.3587429448
Short name T8
Test name
Test status
Simulation time 5240482613 ps
CPU time 22.02 seconds
Started Jul 29 05:01:58 PM PDT 24
Finished Jul 29 05:02:20 PM PDT 24
Peak memory 200532 kb
Host smart-2537c8eb-3c7b-4d4e-a573-0ac534480ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587429448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3587429448
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.392223139
Short name T7
Test name
Test status
Simulation time 149118094 ps
CPU time 1.97 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200228 kb
Host smart-be9c5bd4-bc8d-4f22-900e-cbc55200f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392223139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.392223139
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3111136269
Short name T95
Test name
Test status
Simulation time 1156920711 ps
CPU time 3.28 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 200156 kb
Host smart-22d4947e-4ea7-4f0c-89e8-ad44a290f2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111136269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3111136269
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.178221695
Short name T81
Test name
Test status
Simulation time 16665293018 ps
CPU time 26.31 seconds
Started Jul 29 05:00:00 PM PDT 24
Finished Jul 29 05:00:26 PM PDT 24
Peak memory 218120 kb
Host smart-ce5a90f4-e597-4a79-9a17-34c220fbf36b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178221695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.178221695
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2588853244
Short name T45
Test name
Test status
Simulation time 1231794482 ps
CPU time 5.78 seconds
Started Jul 29 04:59:56 PM PDT 24
Finished Jul 29 05:00:02 PM PDT 24
Peak memory 221488 kb
Host smart-cf6bf734-ecec-4949-b439-5942ee491ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588853244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2588853244
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1880744310
Short name T100
Test name
Test status
Simulation time 303453494 ps
CPU time 2.23 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:38 PM PDT 24
Peak memory 208228 kb
Host smart-7b4650e6-780f-420c-a233-7dcb4d11421c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880744310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1880744310
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3458709750
Short name T24
Test name
Test status
Simulation time 6829836406 ps
CPU time 22.81 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:33 PM PDT 24
Peak memory 200600 kb
Host smart-3147aced-05cf-4b75-9e1f-85beea3ec990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458709750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3458709750
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.73106695
Short name T79
Test name
Test status
Simulation time 54620543 ps
CPU time 0.72 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 199976 kb
Host smart-740db3c4-ef7e-4814-a15f-8650a2235e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73106695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.73106695
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4071412686
Short name T159
Test name
Test status
Simulation time 141236166 ps
CPU time 1.01 seconds
Started Jul 29 04:59:54 PM PDT 24
Finished Jul 29 04:59:55 PM PDT 24
Peak memory 200172 kb
Host smart-a0172480-3fc5-4844-9451-09e9654a3ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071412686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4071412686
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3081404684
Short name T33
Test name
Test status
Simulation time 1215749347 ps
CPU time 5.51 seconds
Started Jul 29 05:01:05 PM PDT 24
Finished Jul 29 05:01:11 PM PDT 24
Peak memory 217612 kb
Host smart-71ee56ac-8525-4671-8dbd-a7386d4fe0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081404684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3081404684
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.830388291
Short name T44
Test name
Test status
Simulation time 185028191 ps
CPU time 1.39 seconds
Started Jul 29 05:02:17 PM PDT 24
Finished Jul 29 05:02:18 PM PDT 24
Peak memory 200180 kb
Host smart-6d99f1b6-1f41-4a18-b205-fa75c7961ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830388291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.830388291
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2652116173
Short name T128
Test name
Test status
Simulation time 415196018 ps
CPU time 1.78 seconds
Started Jul 29 04:55:33 PM PDT 24
Finished Jul 29 04:55:35 PM PDT 24
Peak memory 200032 kb
Host smart-118580b9-3172-4ba3-b50a-c59279c7065e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652116173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2652116173
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.695617466
Short name T72
Test name
Test status
Simulation time 142498278 ps
CPU time 1.23 seconds
Started Jul 29 04:55:10 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 209316 kb
Host smart-a32e7294-be17-4f54-b1e0-e7bd18b5a1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695617466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.695617466
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.239628611
Short name T29
Test name
Test status
Simulation time 2366799516 ps
CPU time 8.27 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:34 PM PDT 24
Peak memory 217600 kb
Host smart-8cc876b5-93f5-4ea1-a7be-4242613f0e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239628611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.239628611
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2340824362
Short name T110
Test name
Test status
Simulation time 222202817 ps
CPU time 1.47 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:55:42 PM PDT 24
Peak memory 200040 kb
Host smart-6ac0cba3-1924-4f1b-b72c-c416ba783700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340824362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2340824362
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1781537886
Short name T9
Test name
Test status
Simulation time 141781147 ps
CPU time 0.85 seconds
Started Jul 29 04:59:53 PM PDT 24
Finished Jul 29 04:59:54 PM PDT 24
Peak memory 199972 kb
Host smart-b27f5a67-58f4-4e12-8d3f-a339090f8ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781537886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1781537886
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.536134084
Short name T149
Test name
Test status
Simulation time 244832271 ps
CPU time 1.04 seconds
Started Jul 29 05:00:09 PM PDT 24
Finished Jul 29 05:00:11 PM PDT 24
Peak memory 217312 kb
Host smart-1dd606d4-1c53-41cb-b1db-894e90d0900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536134084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.536134084
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.804130871
Short name T97
Test name
Test status
Simulation time 903905917 ps
CPU time 2.9 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 200028 kb
Host smart-5bea4738-8124-4290-9a63-251a3d784fae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804130871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
804130871
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4834501
Short name T122
Test name
Test status
Simulation time 504816855 ps
CPU time 1.96 seconds
Started Jul 29 04:55:28 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 200084 kb
Host smart-e77a48e5-176b-4b6c-881c-12f2c31b8b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4834501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.4834501
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1766012296
Short name T548
Test name
Test status
Simulation time 364699210 ps
CPU time 2.33 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 200028 kb
Host smart-c4db25ab-2248-445a-8163-e53b52b40a76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766012296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
766012296
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4245001211
Short name T544
Test name
Test status
Simulation time 267910179 ps
CPU time 3.18 seconds
Started Jul 29 04:55:28 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 200048 kb
Host smart-f52c72f9-635d-4645-9f76-f113ccf4592d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245001211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
245001211
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.234325362
Short name T557
Test name
Test status
Simulation time 142151068 ps
CPU time 0.9 seconds
Started Jul 29 04:55:46 PM PDT 24
Finished Jul 29 04:55:47 PM PDT 24
Peak memory 199908 kb
Host smart-b97d5e2c-53da-4dca-9bee-a433acc4956d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234325362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.234325362
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1398447841
Short name T551
Test name
Test status
Simulation time 123162155 ps
CPU time 1.37 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:09 PM PDT 24
Peak memory 208048 kb
Host smart-25a509b0-ba0b-406d-997c-0fe541b29f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398447841 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1398447841
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.290221706
Short name T554
Test name
Test status
Simulation time 69947353 ps
CPU time 0.77 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 199744 kb
Host smart-89350545-1d83-46d4-836c-09034b39a49b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290221706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.290221706
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1866212991
Short name T614
Test name
Test status
Simulation time 325864228 ps
CPU time 2.76 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:27 PM PDT 24
Peak memory 208208 kb
Host smart-4bd65997-42fc-49bc-b689-f9b95c47ebb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866212991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1866212991
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.599384571
Short name T572
Test name
Test status
Simulation time 159404287 ps
CPU time 1.92 seconds
Started Jul 29 04:55:03 PM PDT 24
Finished Jul 29 04:55:05 PM PDT 24
Peak memory 200008 kb
Host smart-47711f8d-98e9-4f22-8e19-4c5c1cac77af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599384571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.599384571
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.594638150
Short name T562
Test name
Test status
Simulation time 1030203785 ps
CPU time 5.16 seconds
Started Jul 29 04:55:31 PM PDT 24
Finished Jul 29 04:55:37 PM PDT 24
Peak memory 200000 kb
Host smart-76d7b1b3-2a34-4a70-8261-70a029bfd8c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594638150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.594638150
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.753660898
Short name T550
Test name
Test status
Simulation time 91523783 ps
CPU time 0.81 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:10 PM PDT 24
Peak memory 199820 kb
Host smart-b1afa6e2-5785-4d24-8aeb-7f974f7e99ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753660898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.753660898
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.336813478
Short name T588
Test name
Test status
Simulation time 200488883 ps
CPU time 1.34 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:02 PM PDT 24
Peak memory 208140 kb
Host smart-b3375ad6-1782-45ec-a4f5-c0415dd36449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336813478 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.336813478
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.330868760
Short name T592
Test name
Test status
Simulation time 72241861 ps
CPU time 0.83 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:36 PM PDT 24
Peak memory 200004 kb
Host smart-38a2489c-a518-43f3-8f10-0e8c47eb1969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330868760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.330868760
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1685476336
Short name T587
Test name
Test status
Simulation time 77124020 ps
CPU time 0.91 seconds
Started Jul 29 04:55:17 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 199888 kb
Host smart-52d813bf-7e1b-4625-8d41-d560f456d244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685476336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1685476336
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.357715905
Short name T566
Test name
Test status
Simulation time 102871024 ps
CPU time 1.43 seconds
Started Jul 29 04:55:28 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 211456 kb
Host smart-783af1fd-fca2-41a9-b5bf-184c8880df5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357715905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.357715905
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4123484674
Short name T615
Test name
Test status
Simulation time 411573595 ps
CPU time 1.69 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 200044 kb
Host smart-359beac5-8755-451e-8573-d783e6f81a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123484674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4123484674
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1412406616
Short name T565
Test name
Test status
Simulation time 180039106 ps
CPU time 1.88 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:37 PM PDT 24
Peak memory 208392 kb
Host smart-351b46a9-efc7-4fb3-bd68-070c4a4b8d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412406616 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1412406616
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1747056321
Short name T620
Test name
Test status
Simulation time 56900206 ps
CPU time 0.78 seconds
Started Jul 29 04:55:22 PM PDT 24
Finished Jul 29 04:55:23 PM PDT 24
Peak memory 199928 kb
Host smart-524a8bf8-6f62-4e7b-b33b-706252606d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747056321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1747056321
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2769768457
Short name T563
Test name
Test status
Simulation time 102397756 ps
CPU time 1.22 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 199996 kb
Host smart-a739839f-c627-4ff1-982a-5e48607df019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769768457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2769768457
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2222207026
Short name T580
Test name
Test status
Simulation time 90411801 ps
CPU time 1.33 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 208068 kb
Host smart-968b8b38-51ed-4b5f-bc49-62bf6bda7b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222207026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2222207026
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1010775252
Short name T126
Test name
Test status
Simulation time 883670421 ps
CPU time 3.59 seconds
Started Jul 29 04:55:29 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 200096 kb
Host smart-5485b87c-8552-4349-85c0-5927bf9a28aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010775252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1010775252
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2338548406
Short name T584
Test name
Test status
Simulation time 101911980 ps
CPU time 0.86 seconds
Started Jul 29 04:55:44 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 199952 kb
Host smart-131062fc-769e-4bac-add7-ca1fc346e5c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338548406 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2338548406
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3113007715
Short name T570
Test name
Test status
Simulation time 78608173 ps
CPU time 0.81 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 199864 kb
Host smart-9157ae95-36cc-47dd-abb9-f0175cb07db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113007715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3113007715
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3111009929
Short name T115
Test name
Test status
Simulation time 97618365 ps
CPU time 1.18 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 200048 kb
Host smart-c5d6f87b-a7f2-4573-9541-03f5aecec8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111009929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3111009929
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.768002729
Short name T567
Test name
Test status
Simulation time 117081658 ps
CPU time 1.83 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 208172 kb
Host smart-e0c8db3f-78da-4de7-8dc8-98983cb31b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768002729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.768002729
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3424671843
Short name T70
Test name
Test status
Simulation time 489664457 ps
CPU time 1.85 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 200008 kb
Host smart-42410305-1444-4bb2-93d3-00b3104016bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424671843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3424671843
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.939244083
Short name T80
Test name
Test status
Simulation time 182106211 ps
CPU time 1.21 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 209472 kb
Host smart-bda8fa65-72ae-4a96-9a0a-a294ec41de3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939244083 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.939244083
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2374478838
Short name T583
Test name
Test status
Simulation time 65374271 ps
CPU time 0.78 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 199832 kb
Host smart-b4f35592-a060-4dd3-84aa-a28b448efe69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374478838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2374478838
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2267068732
Short name T619
Test name
Test status
Simulation time 73613767 ps
CPU time 0.95 seconds
Started Jul 29 04:55:30 PM PDT 24
Finished Jul 29 04:55:31 PM PDT 24
Peak memory 199836 kb
Host smart-8fcf26a5-529c-419b-9fdf-fba5c2e32c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267068732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2267068732
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.196625228
Short name T606
Test name
Test status
Simulation time 103159158 ps
CPU time 1.32 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 200000 kb
Host smart-d621ca2a-bfc5-4107-9cf1-baafd4928d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196625228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.196625228
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2048005711
Short name T120
Test name
Test status
Simulation time 789623955 ps
CPU time 2.91 seconds
Started Jul 29 04:55:28 PM PDT 24
Finished Jul 29 04:55:31 PM PDT 24
Peak memory 200028 kb
Host smart-be2e4e67-7341-47ac-9d08-91835344acfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048005711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2048005711
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2252280514
Short name T617
Test name
Test status
Simulation time 183826759 ps
CPU time 1.21 seconds
Started Jul 29 04:55:29 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 208256 kb
Host smart-721d5c01-f0ec-4d75-ba4e-7209295069e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252280514 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2252280514
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3259847978
Short name T117
Test name
Test status
Simulation time 54114177 ps
CPU time 0.74 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 199792 kb
Host smart-c4196570-52ae-4d96-82dd-bfc217c52f81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259847978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3259847978
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1164885596
Short name T603
Test name
Test status
Simulation time 77203955 ps
CPU time 0.97 seconds
Started Jul 29 04:55:33 PM PDT 24
Finished Jul 29 04:55:34 PM PDT 24
Peak memory 199924 kb
Host smart-7516a91e-c34e-4e6e-b16c-bf3310987440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164885596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1164885596
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3958171151
Short name T607
Test name
Test status
Simulation time 108915896 ps
CPU time 1.46 seconds
Started Jul 29 04:55:19 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 208192 kb
Host smart-3c86fcaa-3d6a-450d-a8ca-d5f1f834d2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958171151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3958171151
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2283177061
Short name T604
Test name
Test status
Simulation time 923711422 ps
CPU time 3.14 seconds
Started Jul 29 04:55:33 PM PDT 24
Finished Jul 29 04:55:36 PM PDT 24
Peak memory 208040 kb
Host smart-3d182f9d-5020-4d67-b124-87b41dbf363c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283177061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2283177061
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1438308210
Short name T608
Test name
Test status
Simulation time 120146932 ps
CPU time 0.97 seconds
Started Jul 29 04:55:31 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 199932 kb
Host smart-79c882c2-688c-4abb-927b-f7841769d102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438308210 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1438308210
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3670594613
Short name T547
Test name
Test status
Simulation time 75074366 ps
CPU time 0.76 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:40 PM PDT 24
Peak memory 199832 kb
Host smart-96f74b82-fdbd-404c-b97b-ee985b06ab0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670594613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3670594613
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1135241417
Short name T559
Test name
Test status
Simulation time 105021812 ps
CPU time 1.15 seconds
Started Jul 29 04:55:51 PM PDT 24
Finished Jul 29 04:55:52 PM PDT 24
Peak memory 200136 kb
Host smart-7b2d30d3-7354-4048-b3f8-8bda81d458f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135241417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1135241417
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1506315776
Short name T552
Test name
Test status
Simulation time 505584476 ps
CPU time 3.7 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 211256 kb
Host smart-c0d6b6dc-0633-436e-b305-667fd4e4bdb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506315776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1506315776
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2377406155
Short name T560
Test name
Test status
Simulation time 132530322 ps
CPU time 1.29 seconds
Started Jul 29 04:55:52 PM PDT 24
Finished Jul 29 04:55:53 PM PDT 24
Peak memory 208236 kb
Host smart-6a8de08c-8868-4ea9-a3ea-5ed9e43877e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377406155 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2377406155
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3152612824
Short name T573
Test name
Test status
Simulation time 69896354 ps
CPU time 0.81 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 199924 kb
Host smart-04416303-1e24-4e89-85eb-ecd64466b28f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152612824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3152612824
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3930298771
Short name T114
Test name
Test status
Simulation time 98778715 ps
CPU time 1.27 seconds
Started Jul 29 04:55:34 PM PDT 24
Finished Jul 29 04:55:36 PM PDT 24
Peak memory 200084 kb
Host smart-abb74feb-d58a-4b62-bd6f-6a15c904a1c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930298771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3930298771
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.589726042
Short name T125
Test name
Test status
Simulation time 217869544 ps
CPU time 1.51 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:29 PM PDT 24
Peak memory 208220 kb
Host smart-a120703a-7a2d-4928-81f5-29e79fee8c81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589726042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.589726042
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.851892389
Short name T101
Test name
Test status
Simulation time 173946779 ps
CPU time 1.32 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 208228 kb
Host smart-f9a02b9c-35ed-44c6-896b-2475f0b6984d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851892389 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.851892389
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1778314786
Short name T561
Test name
Test status
Simulation time 71399351 ps
CPU time 0.81 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 199708 kb
Host smart-aad6d6b9-be6b-4494-bd91-baa1e6f9d2ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778314786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1778314786
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2426323629
Short name T113
Test name
Test status
Simulation time 237659925 ps
CPU time 1.53 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 200056 kb
Host smart-04234b72-f9e7-4ae7-be5d-2924660ee051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426323629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2426323629
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2506642888
Short name T605
Test name
Test status
Simulation time 268902669 ps
CPU time 1.83 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:37 PM PDT 24
Peak memory 210628 kb
Host smart-2946cfe9-dc7d-427e-a25f-4a866cae4b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506642888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2506642888
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1649658223
Short name T119
Test name
Test status
Simulation time 785361841 ps
CPU time 3.09 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 200060 kb
Host smart-b3b6962f-20df-4b56-8142-563dc677bccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649658223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1649658223
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2205254080
Short name T596
Test name
Test status
Simulation time 231827735 ps
CPU time 1.5 seconds
Started Jul 29 04:55:32 PM PDT 24
Finished Jul 29 04:55:34 PM PDT 24
Peak memory 208228 kb
Host smart-13df227f-67a4-4f64-9a21-9e026e8a0679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205254080 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2205254080
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1556577713
Short name T579
Test name
Test status
Simulation time 63699649 ps
CPU time 0.74 seconds
Started Jul 29 04:55:41 PM PDT 24
Finished Jul 29 04:55:42 PM PDT 24
Peak memory 199988 kb
Host smart-14e806fe-95e3-47e9-8421-736b89b9fca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556577713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1556577713
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3890585629
Short name T111
Test name
Test status
Simulation time 138399351 ps
CPU time 1.07 seconds
Started Jul 29 04:55:34 PM PDT 24
Finished Jul 29 04:55:35 PM PDT 24
Peak memory 199924 kb
Host smart-acafd146-3b21-4283-b2be-dd4d5e845aa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890585629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3890585629
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.466549656
Short name T577
Test name
Test status
Simulation time 176446034 ps
CPU time 2.44 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 208232 kb
Host smart-9e8dcab6-95f6-4ffb-aca2-1906944f221b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466549656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.466549656
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3649404972
Short name T135
Test name
Test status
Simulation time 425159627 ps
CPU time 1.71 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:37 PM PDT 24
Peak memory 200060 kb
Host smart-fbf6b2e1-2dff-4215-9036-dde62189bcc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649404972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3649404972
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.331580995
Short name T96
Test name
Test status
Simulation time 126911490 ps
CPU time 0.95 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:50 PM PDT 24
Peak memory 200052 kb
Host smart-892df5eb-fc03-4d39-84dc-ead293994bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331580995 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.331580995
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.51564336
Short name T612
Test name
Test status
Simulation time 72741060 ps
CPU time 0.82 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 199916 kb
Host smart-f436dfb2-5c9d-4693-805c-3cc6cc0140df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51564336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.51564336
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2831245215
Short name T600
Test name
Test status
Simulation time 127313893 ps
CPU time 1.33 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:55:42 PM PDT 24
Peak memory 200016 kb
Host smart-792f1618-e36c-4378-a62a-9513f1adcbf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831245215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2831245215
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3201872332
Short name T571
Test name
Test status
Simulation time 922546148 ps
CPU time 2.98 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:52 PM PDT 24
Peak memory 200068 kb
Host smart-db60ca32-74e5-4d84-a358-f0398534bb42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201872332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3201872332
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.891029336
Short name T556
Test name
Test status
Simulation time 128150297 ps
CPU time 1.04 seconds
Started Jul 29 04:55:37 PM PDT 24
Finished Jul 29 04:55:38 PM PDT 24
Peak memory 208204 kb
Host smart-2d327178-c7c4-46f4-be37-729d541bd20a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891029336 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.891029336
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3587614021
Short name T69
Test name
Test status
Simulation time 68120035 ps
CPU time 0.81 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 199900 kb
Host smart-5dd31ec7-8e1c-45c2-b4ed-e142bf9af2d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587614021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3587614021
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3819355683
Short name T616
Test name
Test status
Simulation time 129775151 ps
CPU time 1.08 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 199952 kb
Host smart-ef7e5e85-a2f5-4364-8d70-239438a513f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819355683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3819355683
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4041130569
Short name T98
Test name
Test status
Simulation time 317958965 ps
CPU time 2.28 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:41 PM PDT 24
Peak memory 208212 kb
Host smart-1182b92f-7750-46ce-9ca2-5c8b4ab2fb6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041130569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4041130569
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.670052970
Short name T71
Test name
Test status
Simulation time 935921512 ps
CPU time 3.09 seconds
Started Jul 29 04:55:37 PM PDT 24
Finished Jul 29 04:55:40 PM PDT 24
Peak memory 200040 kb
Host smart-770f7c91-dee5-437d-8d76-e33576cc2b45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670052970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.670052970
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1098655395
Short name T553
Test name
Test status
Simulation time 360863844 ps
CPU time 2.29 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:23 PM PDT 24
Peak memory 200028 kb
Host smart-6716143a-87da-4792-b90a-468874b333db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098655395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
098655395
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.942709047
Short name T68
Test name
Test status
Simulation time 1546464079 ps
CPU time 8.62 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 200004 kb
Host smart-22a52280-524f-4685-bb0e-aec33889f114
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942709047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.942709047
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2895310123
Short name T589
Test name
Test status
Simulation time 99989993 ps
CPU time 0.8 seconds
Started Jul 29 04:55:57 PM PDT 24
Finished Jul 29 04:55:58 PM PDT 24
Peak memory 199908 kb
Host smart-08fd12ac-d426-480a-8bd4-0922fc6ba27b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895310123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
895310123
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1557993954
Short name T558
Test name
Test status
Simulation time 115665538 ps
CPU time 1.02 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 200348 kb
Host smart-3876d945-8fd5-4d3b-92b2-ca7591e035ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557993954 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1557993954
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3609955102
Short name T568
Test name
Test status
Simulation time 90456735 ps
CPU time 0.86 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 199868 kb
Host smart-3c80ead0-9df7-4b5e-8577-acad3a782437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609955102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3609955102
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2062903212
Short name T601
Test name
Test status
Simulation time 135200399 ps
CPU time 1.09 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 199928 kb
Host smart-a956a63b-b7e4-4112-8a5a-509abd01b5a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062903212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2062903212
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3764561624
Short name T582
Test name
Test status
Simulation time 757985305 ps
CPU time 2.81 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:14 PM PDT 24
Peak memory 199996 kb
Host smart-7b945efe-2f47-4df5-89c2-a4aa1c22f99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764561624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3764561624
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1187030508
Short name T578
Test name
Test status
Simulation time 159910517 ps
CPU time 2.13 seconds
Started Jul 29 04:55:37 PM PDT 24
Finished Jul 29 04:55:39 PM PDT 24
Peak memory 200068 kb
Host smart-18d90ca9-4a28-460e-bb21-78acba12fa7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187030508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
187030508
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.801876157
Short name T613
Test name
Test status
Simulation time 803583741 ps
CPU time 4.59 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:05 PM PDT 24
Peak memory 199924 kb
Host smart-d7275ba9-e23f-45c9-9822-e03df4fe4935
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801876157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.801876157
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1429178104
Short name T543
Test name
Test status
Simulation time 141818061 ps
CPU time 1.01 seconds
Started Jul 29 04:55:31 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 199920 kb
Host smart-b98c08e8-e85e-45a2-8dd5-460602311d2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429178104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
429178104
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1445334165
Short name T564
Test name
Test status
Simulation time 178957826 ps
CPU time 1.63 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 208248 kb
Host smart-5890570a-d06a-444f-b336-8df2e9d7e857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445334165 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1445334165
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1936032266
Short name T118
Test name
Test status
Simulation time 74987580 ps
CPU time 0.81 seconds
Started Jul 29 04:55:13 PM PDT 24
Finished Jul 29 04:55:14 PM PDT 24
Peak memory 199824 kb
Host smart-b72cbb48-c9d9-4d71-9750-f44030ba7e34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936032266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1936032266
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3791843878
Short name T586
Test name
Test status
Simulation time 236705915 ps
CPU time 1.51 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 200416 kb
Host smart-db8abdff-adf7-451b-bf57-bfda91c8ab19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791843878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3791843878
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2339189263
Short name T73
Test name
Test status
Simulation time 271735189 ps
CPU time 2.09 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 210672 kb
Host smart-8471aa3e-41fc-4d37-a3d0-d8a04936d013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339189263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2339189263
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3867560607
Short name T123
Test name
Test status
Simulation time 890958065 ps
CPU time 3.18 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 199980 kb
Host smart-fd0b7b28-18cf-4c60-815b-87ec877b4f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867560607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3867560607
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2510877910
Short name T610
Test name
Test status
Simulation time 148994969 ps
CPU time 1.92 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:27 PM PDT 24
Peak memory 208180 kb
Host smart-52ddb881-a3b5-4606-8c03-203aaa0e2d34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510877910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
510877910
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4225257414
Short name T545
Test name
Test status
Simulation time 1559926773 ps
CPU time 8.63 seconds
Started Jul 29 04:55:30 PM PDT 24
Finished Jul 29 04:55:39 PM PDT 24
Peak memory 200096 kb
Host smart-bdc89742-28fa-4709-a0f3-b9c35abe7a8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225257414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
225257414
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.370169770
Short name T546
Test name
Test status
Simulation time 94446546 ps
CPU time 0.84 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 199920 kb
Host smart-a92bfcb4-4bbb-4937-933d-3f04285c0699
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370169770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.370169770
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1552902642
Short name T569
Test name
Test status
Simulation time 116790291 ps
CPU time 0.94 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 200012 kb
Host smart-70ea33ee-15b2-4140-9fb7-b2a30d2e117e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552902642 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1552902642
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3477731631
Short name T611
Test name
Test status
Simulation time 91862187 ps
CPU time 0.9 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 199904 kb
Host smart-522ae1b2-d96a-4c37-b8d9-0e98d6211e50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477731631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3477731631
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2893594318
Short name T109
Test name
Test status
Simulation time 256246634 ps
CPU time 1.53 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 199956 kb
Host smart-fabbc6bb-c018-49d8-82a1-a7dcaf3af232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893594318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2893594318
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2470955699
Short name T124
Test name
Test status
Simulation time 557866917 ps
CPU time 3.63 seconds
Started Jul 29 04:55:31 PM PDT 24
Finished Jul 29 04:55:35 PM PDT 24
Peak memory 208164 kb
Host smart-0cb215b4-dfa1-468c-b1b9-de675a4c9310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470955699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2470955699
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1670345696
Short name T602
Test name
Test status
Simulation time 830863308 ps
CPU time 2.87 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 200072 kb
Host smart-df91aee5-9985-4d50-87de-2206f90d5ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670345696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1670345696
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3008045639
Short name T609
Test name
Test status
Simulation time 194941696 ps
CPU time 1.22 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 208256 kb
Host smart-b21aba26-b8fd-4c9d-99a3-09b0c6b6552d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008045639 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3008045639
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3799373741
Short name T116
Test name
Test status
Simulation time 58321824 ps
CPU time 0.73 seconds
Started Jul 29 04:55:01 PM PDT 24
Finished Jul 29 04:55:02 PM PDT 24
Peak memory 199792 kb
Host smart-c29d6c80-a14c-4f62-852a-2550c9bb6661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799373741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3799373741
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2478909684
Short name T595
Test name
Test status
Simulation time 134456323 ps
CPU time 1.12 seconds
Started Jul 29 04:55:26 PM PDT 24
Finished Jul 29 04:55:27 PM PDT 24
Peak memory 199996 kb
Host smart-ab8a71ff-9a6c-42bb-89fd-59ccc2ce44af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478909684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2478909684
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.204968454
Short name T581
Test name
Test status
Simulation time 231913222 ps
CPU time 1.83 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 208132 kb
Host smart-a1b1f509-7885-437c-b652-dbca99a31f56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204968454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.204968454
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1032491196
Short name T597
Test name
Test status
Simulation time 881079492 ps
CPU time 2.88 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:19 PM PDT 24
Peak memory 199948 kb
Host smart-d80adcbb-ac67-475f-8533-8b2e3a5681a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032491196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1032491196
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3111858365
Short name T574
Test name
Test status
Simulation time 216237902 ps
CPU time 1.45 seconds
Started Jul 29 04:55:40 PM PDT 24
Finished Jul 29 04:55:42 PM PDT 24
Peak memory 208184 kb
Host smart-49242817-59f3-4f48-b349-13d5d3d6ce8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111858365 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3111858365
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2949152589
Short name T576
Test name
Test status
Simulation time 60568344 ps
CPU time 0.86 seconds
Started Jul 29 04:55:36 PM PDT 24
Finished Jul 29 04:55:37 PM PDT 24
Peak memory 199820 kb
Host smart-56a4009f-36b6-447f-8f60-f6cd4cc80624
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949152589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2949152589
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3844309784
Short name T575
Test name
Test status
Simulation time 137780288 ps
CPU time 1.26 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 200088 kb
Host smart-661d0128-3093-46d1-8d6b-04222005a40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844309784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3844309784
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2248839549
Short name T599
Test name
Test status
Simulation time 132744956 ps
CPU time 2 seconds
Started Jul 29 04:55:29 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 208220 kb
Host smart-33262614-7ab6-43a6-b9ce-7884b7a1314b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248839549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2248839549
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4277108741
Short name T99
Test name
Test status
Simulation time 208034705 ps
CPU time 1.41 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 208276 kb
Host smart-739aeb43-255d-46c7-84a4-a2e24fe06224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277108741 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4277108741
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.21655951
Short name T590
Test name
Test status
Simulation time 76481645 ps
CPU time 0.81 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:40 PM PDT 24
Peak memory 199724 kb
Host smart-1e20d71a-e59f-4463-9f23-db8b2c529e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.21655951
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1615517771
Short name T555
Test name
Test status
Simulation time 187571995 ps
CPU time 1.5 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 199996 kb
Host smart-33405fb5-f5fc-4003-aa86-6e8dd96e43d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615517771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1615517771
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2361486925
Short name T598
Test name
Test status
Simulation time 193283766 ps
CPU time 2.96 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 208208 kb
Host smart-e1b696df-334c-4ea4-a3a4-39702dc8b22a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361486925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2361486925
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2946295689
Short name T121
Test name
Test status
Simulation time 424946937 ps
CPU time 1.71 seconds
Started Jul 29 04:55:38 PM PDT 24
Finished Jul 29 04:55:39 PM PDT 24
Peak memory 200060 kb
Host smart-3d845503-06aa-4cb9-9a67-5704e2f4a601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946295689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2946295689
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.285310864
Short name T618
Test name
Test status
Simulation time 116774321 ps
CPU time 1.16 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 208236 kb
Host smart-021d3d6a-13d5-4757-af37-daa27fbdb8a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285310864 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.285310864
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3960148059
Short name T112
Test name
Test status
Simulation time 64564606 ps
CPU time 0.74 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 199852 kb
Host smart-b3ee3e7b-7eef-4e51-8ecb-40b7109e7ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960148059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3960148059
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2297807232
Short name T591
Test name
Test status
Simulation time 243620620 ps
CPU time 1.61 seconds
Started Jul 29 04:55:37 PM PDT 24
Finished Jul 29 04:55:39 PM PDT 24
Peak memory 199972 kb
Host smart-7285a40a-0725-4e0b-b77b-4f40990d8e0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297807232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2297807232
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3825351800
Short name T594
Test name
Test status
Simulation time 165779397 ps
CPU time 2.26 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:38 PM PDT 24
Peak memory 211492 kb
Host smart-20faf4ca-5221-44df-bf15-c31a7410b59b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825351800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3825351800
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4134655260
Short name T134
Test name
Test status
Simulation time 522667023 ps
CPU time 1.85 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:52 PM PDT 24
Peak memory 200112 kb
Host smart-50b9b15f-658e-4026-8c7f-6bfa9fdde512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134655260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.4134655260
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2672642233
Short name T549
Test name
Test status
Simulation time 184731575 ps
CPU time 1.21 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 208120 kb
Host smart-5460f2bc-1049-4193-a567-b147f3090a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672642233 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2672642233
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2652517799
Short name T585
Test name
Test status
Simulation time 66239233 ps
CPU time 0.81 seconds
Started Jul 29 04:55:33 PM PDT 24
Finished Jul 29 04:55:34 PM PDT 24
Peak memory 199684 kb
Host smart-17e8206e-9b74-4718-8f64-75a97fb8a3c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652517799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2652517799
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3000585222
Short name T593
Test name
Test status
Simulation time 154649446 ps
CPU time 1.1 seconds
Started Jul 29 04:55:19 PM PDT 24
Finished Jul 29 04:55:20 PM PDT 24
Peak memory 200000 kb
Host smart-8aef53ac-8178-4f2b-9625-a125401dcd25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000585222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3000585222
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1499535125
Short name T74
Test name
Test status
Simulation time 529318086 ps
CPU time 3.28 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:53 PM PDT 24
Peak memory 212004 kb
Host smart-8f2200d0-90ac-42c2-b156-5ca48677fec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499535125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1499535125
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3605263914
Short name T127
Test name
Test status
Simulation time 532612265 ps
CPU time 1.91 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 200132 kb
Host smart-85d7c97a-62e2-4c6f-93a7-672747598b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605263914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3605263914
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3659089919
Short name T233
Test name
Test status
Simulation time 66649079 ps
CPU time 0.8 seconds
Started Jul 29 05:00:02 PM PDT 24
Finished Jul 29 05:00:06 PM PDT 24
Peak memory 200104 kb
Host smart-432df5d1-a5e6-455c-9941-7e9cf33cb5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659089919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3659089919
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3800038840
Short name T221
Test name
Test status
Simulation time 244743498 ps
CPU time 1.11 seconds
Started Jul 29 04:59:57 PM PDT 24
Finished Jul 29 04:59:58 PM PDT 24
Peak memory 217332 kb
Host smart-3d8a1c8d-a5f9-4d8f-b54f-cfaad68c7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800038840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3800038840
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3398557306
Short name T217
Test name
Test status
Simulation time 768038891 ps
CPU time 4.12 seconds
Started Jul 29 04:59:57 PM PDT 24
Finished Jul 29 05:00:01 PM PDT 24
Peak memory 200384 kb
Host smart-791000b6-e0ba-4897-ae02-1b6b92d25c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398557306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3398557306
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1688823250
Short name T496
Test name
Test status
Simulation time 188732402 ps
CPU time 1.37 seconds
Started Jul 29 04:59:50 PM PDT 24
Finished Jul 29 04:59:51 PM PDT 24
Peak memory 200284 kb
Host smart-f34487e5-926d-4edb-a3ab-c0906ba37813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688823250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1688823250
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2755795174
Short name T430
Test name
Test status
Simulation time 636239079 ps
CPU time 2.55 seconds
Started Jul 29 05:00:03 PM PDT 24
Finished Jul 29 05:00:08 PM PDT 24
Peak memory 200316 kb
Host smart-8b921a38-8651-4e82-b94b-202dc89397b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755795174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2755795174
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2140077942
Short name T313
Test name
Test status
Simulation time 554538690 ps
CPU time 3.01 seconds
Started Jul 29 04:59:55 PM PDT 24
Finished Jul 29 04:59:58 PM PDT 24
Peak memory 200220 kb
Host smart-12e5a4f9-c950-435b-a0d4-dac62d621dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140077942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2140077942
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2689664640
Short name T479
Test name
Test status
Simulation time 277619108 ps
CPU time 1.55 seconds
Started Jul 29 04:59:55 PM PDT 24
Finished Jul 29 04:59:57 PM PDT 24
Peak memory 200284 kb
Host smart-3d7f3bd0-2037-45c7-905e-949854f362d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689664640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2689664640
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4199167790
Short name T481
Test name
Test status
Simulation time 62404586 ps
CPU time 0.77 seconds
Started Jul 29 05:00:05 PM PDT 24
Finished Jul 29 05:00:06 PM PDT 24
Peak memory 199928 kb
Host smart-027bb8f2-af91-4f65-84ce-fdce5301e910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199167790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4199167790
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3820912738
Short name T506
Test name
Test status
Simulation time 1219919839 ps
CPU time 6.01 seconds
Started Jul 29 05:00:06 PM PDT 24
Finished Jul 29 05:00:12 PM PDT 24
Peak memory 221556 kb
Host smart-8fb3ab5c-c526-4f1a-9dd9-a4909901a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820912738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3820912738
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2180732732
Short name T162
Test name
Test status
Simulation time 130787239 ps
CPU time 0.88 seconds
Started Jul 29 05:00:03 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 199964 kb
Host smart-a8af23ff-0bed-4ff0-b7b9-f331cc7d5e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180732732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2180732732
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2851259365
Short name T274
Test name
Test status
Simulation time 1401287311 ps
CPU time 5.5 seconds
Started Jul 29 05:00:03 PM PDT 24
Finished Jul 29 05:00:11 PM PDT 24
Peak memory 200384 kb
Host smart-5f02227d-8c4b-4a96-aaf0-cc6f37bbcd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851259365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2851259365
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2359452161
Short name T75
Test name
Test status
Simulation time 19332926559 ps
CPU time 30.04 seconds
Started Jul 29 05:00:09 PM PDT 24
Finished Jul 29 05:00:39 PM PDT 24
Peak memory 217128 kb
Host smart-5bb5fea6-b2ba-4644-bc5f-fce44a49695f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359452161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2359452161
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4142349738
Short name T5
Test name
Test status
Simulation time 145152432 ps
CPU time 1.11 seconds
Started Jul 29 05:00:02 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 200116 kb
Host smart-82ae6f93-3526-4171-b16a-2adbc9b34dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142349738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4142349738
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2625367614
Short name T11
Test name
Test status
Simulation time 202197351 ps
CPU time 1.37 seconds
Started Jul 29 05:00:02 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 200280 kb
Host smart-d3bc523d-67f4-4dc4-bb28-b903e7a2702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625367614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2625367614
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1343130658
Short name T227
Test name
Test status
Simulation time 3384339681 ps
CPU time 16.47 seconds
Started Jul 29 05:00:05 PM PDT 24
Finished Jul 29 05:00:22 PM PDT 24
Peak memory 200536 kb
Host smart-b3a7134d-51ed-4100-a318-69ec1341df2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343130658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1343130658
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2199503448
Short name T258
Test name
Test status
Simulation time 129899770 ps
CPU time 1.57 seconds
Started Jul 29 05:00:02 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 200128 kb
Host smart-dbd4fac6-cb89-4a25-ae47-0b3469e164ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199503448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2199503448
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3386356198
Short name T404
Test name
Test status
Simulation time 139232305 ps
CPU time 0.98 seconds
Started Jul 29 05:00:03 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 200104 kb
Host smart-8fbcea6e-dbee-4a44-9b07-5a3e60e2436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386356198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3386356198
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.513641446
Short name T335
Test name
Test status
Simulation time 72396508 ps
CPU time 0.82 seconds
Started Jul 29 05:01:11 PM PDT 24
Finished Jul 29 05:01:12 PM PDT 24
Peak memory 199992 kb
Host smart-37022051-5a06-4b03-a542-5cfeff574f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513641446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.513641446
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.462161722
Short name T329
Test name
Test status
Simulation time 1230582793 ps
CPU time 5.79 seconds
Started Jul 29 05:00:59 PM PDT 24
Finished Jul 29 05:01:05 PM PDT 24
Peak memory 217556 kb
Host smart-78a13b2b-2bfc-45a3-aaf0-d70f4b71e9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462161722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.462161722
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4206257175
Short name T364
Test name
Test status
Simulation time 244570439 ps
CPU time 1.29 seconds
Started Jul 29 05:01:01 PM PDT 24
Finished Jul 29 05:01:02 PM PDT 24
Peak memory 217456 kb
Host smart-bf2abded-26b4-48c2-ac2e-be8affe36465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206257175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4206257175
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4100397063
Short name T382
Test name
Test status
Simulation time 237284731 ps
CPU time 0.96 seconds
Started Jul 29 05:01:02 PM PDT 24
Finished Jul 29 05:01:03 PM PDT 24
Peak memory 200020 kb
Host smart-76a8da90-3af5-49ae-b6c0-405840f363c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100397063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4100397063
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3070291734
Short name T178
Test name
Test status
Simulation time 1384465683 ps
CPU time 5.31 seconds
Started Jul 29 05:00:57 PM PDT 24
Finished Jul 29 05:01:02 PM PDT 24
Peak memory 200408 kb
Host smart-46de728b-37a4-4a61-b3ae-9e15a5a03a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070291734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3070291734
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3743012422
Short name T456
Test name
Test status
Simulation time 166028147 ps
CPU time 1.17 seconds
Started Jul 29 05:00:59 PM PDT 24
Finished Jul 29 05:01:01 PM PDT 24
Peak memory 200108 kb
Host smart-6f35ce68-495d-4912-8b56-3dfebf205e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743012422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3743012422
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3718352689
Short name T52
Test name
Test status
Simulation time 123534070 ps
CPU time 1.2 seconds
Started Jul 29 05:00:58 PM PDT 24
Finished Jul 29 05:00:59 PM PDT 24
Peak memory 200412 kb
Host smart-18730ce8-acf2-4891-b23c-39465522a621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718352689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3718352689
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3514793451
Short name T155
Test name
Test status
Simulation time 6291712307 ps
CPU time 24.38 seconds
Started Jul 29 05:01:00 PM PDT 24
Finished Jul 29 05:01:24 PM PDT 24
Peak memory 208620 kb
Host smart-49bdb06e-e609-4a7b-af8b-420ae59b096a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514793451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3514793451
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3162418594
Short name T212
Test name
Test status
Simulation time 511118652 ps
CPU time 2.7 seconds
Started Jul 29 05:00:58 PM PDT 24
Finished Jul 29 05:01:01 PM PDT 24
Peak memory 200204 kb
Host smart-c26c9122-5b8a-460d-b4f0-f5f9d491a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162418594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3162418594
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.445348198
Short name T38
Test name
Test status
Simulation time 162952299 ps
CPU time 1.38 seconds
Started Jul 29 05:01:00 PM PDT 24
Finished Jul 29 05:01:02 PM PDT 24
Peak memory 200260 kb
Host smart-616b5f80-edf2-455b-87e7-bc454faaa853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445348198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.445348198
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.169196819
Short name T460
Test name
Test status
Simulation time 72943738 ps
CPU time 0.77 seconds
Started Jul 29 05:01:14 PM PDT 24
Finished Jul 29 05:01:15 PM PDT 24
Peak memory 200052 kb
Host smart-a6fd3839-5159-4beb-91e4-757202c1c32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169196819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.169196819
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1176019611
Short name T59
Test name
Test status
Simulation time 247498318 ps
CPU time 1.04 seconds
Started Jul 29 05:01:11 PM PDT 24
Finished Jul 29 05:01:13 PM PDT 24
Peak memory 217444 kb
Host smart-e0873a9c-6a8a-46dd-9ff3-5b2884acbf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176019611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1176019611
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.228534783
Short name T251
Test name
Test status
Simulation time 96073734 ps
CPU time 0.78 seconds
Started Jul 29 05:01:07 PM PDT 24
Finished Jul 29 05:01:07 PM PDT 24
Peak memory 200020 kb
Host smart-06eed360-21ef-4193-b4a0-c07ecc8248cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228534783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.228534783
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4188409790
Short name T88
Test name
Test status
Simulation time 1013490060 ps
CPU time 4.87 seconds
Started Jul 29 05:01:06 PM PDT 24
Finished Jul 29 05:01:11 PM PDT 24
Peak memory 200540 kb
Host smart-ffa91822-9a45-47bd-add7-24bff79322a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188409790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4188409790
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2452617195
Short name T373
Test name
Test status
Simulation time 191235607 ps
CPU time 1.33 seconds
Started Jul 29 05:01:06 PM PDT 24
Finished Jul 29 05:01:08 PM PDT 24
Peak memory 200244 kb
Host smart-8135601a-5223-4609-b41a-e9a8c96fa38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452617195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2452617195
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.87743520
Short name T437
Test name
Test status
Simulation time 127113116 ps
CPU time 1.21 seconds
Started Jul 29 05:01:06 PM PDT 24
Finished Jul 29 05:01:07 PM PDT 24
Peak memory 200228 kb
Host smart-02a44ec9-85db-46b1-adc5-b68026fb7851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87743520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.87743520
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3997585340
Short name T443
Test name
Test status
Simulation time 3711569745 ps
CPU time 15.47 seconds
Started Jul 29 05:01:12 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 200436 kb
Host smart-9b219c71-c366-49cc-aac1-9694e2dd1250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997585340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3997585340
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1300765080
Short name T176
Test name
Test status
Simulation time 435942171 ps
CPU time 2.43 seconds
Started Jul 29 05:01:05 PM PDT 24
Finished Jul 29 05:01:08 PM PDT 24
Peak memory 208248 kb
Host smart-a3317e7d-26c1-429d-9e66-44ff68c42ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300765080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1300765080
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3910300976
Short name T452
Test name
Test status
Simulation time 116581346 ps
CPU time 1.04 seconds
Started Jul 29 05:01:07 PM PDT 24
Finished Jul 29 05:01:08 PM PDT 24
Peak memory 200148 kb
Host smart-88a03368-705d-48f6-93cb-b5abd411d991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910300976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3910300976
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2530730781
Short name T533
Test name
Test status
Simulation time 66575399 ps
CPU time 0.77 seconds
Started Jul 29 05:01:17 PM PDT 24
Finished Jul 29 05:01:18 PM PDT 24
Peak memory 199972 kb
Host smart-a18f4c2a-4226-45d6-9584-d3aa336b1da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530730781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2530730781
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3268288033
Short name T374
Test name
Test status
Simulation time 2360291881 ps
CPU time 9.04 seconds
Started Jul 29 05:01:12 PM PDT 24
Finished Jul 29 05:01:21 PM PDT 24
Peak memory 217840 kb
Host smart-638b2b2c-395e-4c17-89bd-a7490ad43fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268288033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3268288033
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.956245112
Short name T211
Test name
Test status
Simulation time 246075648 ps
CPU time 1.07 seconds
Started Jul 29 05:01:17 PM PDT 24
Finished Jul 29 05:01:18 PM PDT 24
Peak memory 217432 kb
Host smart-53b03987-6283-44d7-af01-6c5c44525bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956245112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.956245112
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.234345713
Short name T516
Test name
Test status
Simulation time 135451305 ps
CPU time 0.82 seconds
Started Jul 29 05:01:11 PM PDT 24
Finished Jul 29 05:01:12 PM PDT 24
Peak memory 199980 kb
Host smart-9ae82025-7f29-4ee5-8cba-d14e020fd01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234345713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.234345713
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.4021022316
Short name T448
Test name
Test status
Simulation time 1103536623 ps
CPU time 5.91 seconds
Started Jul 29 05:01:13 PM PDT 24
Finished Jul 29 05:01:19 PM PDT 24
Peak memory 200544 kb
Host smart-26f6c23c-5428-4320-a2da-329c9feabb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021022316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4021022316
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.272171892
Short name T170
Test name
Test status
Simulation time 178859947 ps
CPU time 1.26 seconds
Started Jul 29 05:01:12 PM PDT 24
Finished Jul 29 05:01:13 PM PDT 24
Peak memory 200176 kb
Host smart-9f11c611-4340-4380-8b84-76b765c299d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272171892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.272171892
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.796050329
Short name T342
Test name
Test status
Simulation time 115327234 ps
CPU time 1.31 seconds
Started Jul 29 05:01:12 PM PDT 24
Finished Jul 29 05:01:13 PM PDT 24
Peak memory 200296 kb
Host smart-43896e59-7f23-4801-94f8-5c716723a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796050329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.796050329
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.633960212
Short name T518
Test name
Test status
Simulation time 6008457958 ps
CPU time 23.58 seconds
Started Jul 29 05:01:19 PM PDT 24
Finished Jul 29 05:01:43 PM PDT 24
Peak memory 209424 kb
Host smart-3ac32042-41db-4c52-9f23-c1c6a3ba9da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633960212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.633960212
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.750520647
Short name T190
Test name
Test status
Simulation time 376039087 ps
CPU time 2.41 seconds
Started Jul 29 05:01:12 PM PDT 24
Finished Jul 29 05:01:15 PM PDT 24
Peak memory 208280 kb
Host smart-171e684d-bf80-4c87-8a05-905315f0ca7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750520647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.750520647
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1372069961
Short name T157
Test name
Test status
Simulation time 109105765 ps
CPU time 1.01 seconds
Started Jul 29 05:01:13 PM PDT 24
Finished Jul 29 05:01:14 PM PDT 24
Peak memory 200284 kb
Host smart-8615bba7-40e2-4c7e-af22-a20b5d8190a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372069961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1372069961
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.53346857
Short name T158
Test name
Test status
Simulation time 66320388 ps
CPU time 0.76 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 199940 kb
Host smart-e1a96cfe-ebd7-4b95-bfbd-84e3b6748f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53346857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.53346857
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2018197664
Short name T447
Test name
Test status
Simulation time 1231630485 ps
CPU time 5.65 seconds
Started Jul 29 05:01:18 PM PDT 24
Finished Jul 29 05:01:24 PM PDT 24
Peak memory 221444 kb
Host smart-0933baae-95cc-4ad8-98c9-83c7c8041621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018197664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2018197664
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3625377548
Short name T93
Test name
Test status
Simulation time 244741833 ps
CPU time 1.1 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 217336 kb
Host smart-8a101aa1-7a66-4a1e-8f8d-82be24d4bdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625377548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3625377548
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.716461340
Short name T247
Test name
Test status
Simulation time 222531223 ps
CPU time 0.98 seconds
Started Jul 29 05:01:19 PM PDT 24
Finished Jul 29 05:01:20 PM PDT 24
Peak memory 200080 kb
Host smart-21cbb56f-eb4e-4c6c-adac-9bff13d67099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716461340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.716461340
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.638909113
Short name T209
Test name
Test status
Simulation time 868784641 ps
CPU time 4.44 seconds
Started Jul 29 05:01:18 PM PDT 24
Finished Jul 29 05:01:23 PM PDT 24
Peak memory 200428 kb
Host smart-f1a3d233-6daf-415c-8c28-ba663c00c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638909113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.638909113
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2385443575
Short name T385
Test name
Test status
Simulation time 97481720 ps
CPU time 0.97 seconds
Started Jul 29 05:01:18 PM PDT 24
Finished Jul 29 05:01:19 PM PDT 24
Peak memory 200268 kb
Host smart-6ae5c872-6887-45db-b0a6-ab44bb4b1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385443575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2385443575
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3200032149
Short name T245
Test name
Test status
Simulation time 119150900 ps
CPU time 1.21 seconds
Started Jul 29 05:01:18 PM PDT 24
Finished Jul 29 05:01:20 PM PDT 24
Peak memory 200628 kb
Host smart-7a6951c7-1211-4a03-a4f3-575d3e7d4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200032149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3200032149
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.4133659968
Short name T295
Test name
Test status
Simulation time 361460300 ps
CPU time 2.16 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:01:33 PM PDT 24
Peak memory 200104 kb
Host smart-d4b59682-ab06-42c2-92e3-50baabd83f62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133659968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4133659968
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2406821092
Short name T142
Test name
Test status
Simulation time 141533915 ps
CPU time 1.76 seconds
Started Jul 29 05:01:18 PM PDT 24
Finished Jul 29 05:01:20 PM PDT 24
Peak memory 200080 kb
Host smart-a664caaa-a637-4cc4-a460-40b41e883c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406821092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2406821092
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1174495991
Short name T417
Test name
Test status
Simulation time 98077593 ps
CPU time 0.94 seconds
Started Jul 29 05:01:18 PM PDT 24
Finished Jul 29 05:01:19 PM PDT 24
Peak memory 200140 kb
Host smart-113cb60c-13f2-443b-a05c-8a1df74617ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174495991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1174495991
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2261364031
Short name T63
Test name
Test status
Simulation time 1223995379 ps
CPU time 5.78 seconds
Started Jul 29 05:01:29 PM PDT 24
Finished Jul 29 05:01:35 PM PDT 24
Peak memory 217600 kb
Host smart-b5933e14-907f-4d47-99ff-f33788b50e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261364031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2261364031
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1379287836
Short name T343
Test name
Test status
Simulation time 244450847 ps
CPU time 1.08 seconds
Started Jul 29 05:01:27 PM PDT 24
Finished Jul 29 05:01:28 PM PDT 24
Peak memory 217432 kb
Host smart-f3662f63-3d24-47d7-8a36-cabea871803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379287836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1379287836
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2400286310
Short name T273
Test name
Test status
Simulation time 171241012 ps
CPU time 0.84 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:26 PM PDT 24
Peak memory 199976 kb
Host smart-efc264d7-368a-4a66-9daf-b421d3310cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400286310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2400286310
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2228649221
Short name T350
Test name
Test status
Simulation time 1391616220 ps
CPU time 5.69 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:31 PM PDT 24
Peak memory 200536 kb
Host smart-b57a398e-375e-4646-b783-7e89c12501c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228649221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2228649221
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1141778271
Short name T238
Test name
Test status
Simulation time 167486220 ps
CPU time 1.25 seconds
Started Jul 29 05:01:24 PM PDT 24
Finished Jul 29 05:01:25 PM PDT 24
Peak memory 200128 kb
Host smart-07bf99da-9324-4c10-ac4f-5ead2032b381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141778271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1141778271
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2656956272
Short name T420
Test name
Test status
Simulation time 202323184 ps
CPU time 1.53 seconds
Started Jul 29 05:01:28 PM PDT 24
Finished Jul 29 05:01:29 PM PDT 24
Peak memory 200368 kb
Host smart-ac56727e-ea7d-42d3-bf3b-d468b7d0918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656956272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2656956272
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.889337390
Short name T51
Test name
Test status
Simulation time 10159114117 ps
CPU time 36.38 seconds
Started Jul 29 05:01:28 PM PDT 24
Finished Jul 29 05:02:05 PM PDT 24
Peak memory 208760 kb
Host smart-ed243e8f-66ee-43ed-a1eb-eae2a8399849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889337390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.889337390
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2263994635
Short name T232
Test name
Test status
Simulation time 269607968 ps
CPU time 1.88 seconds
Started Jul 29 05:01:23 PM PDT 24
Finished Jul 29 05:01:25 PM PDT 24
Peak memory 200180 kb
Host smart-c69b0f59-c1a4-4486-b52e-9293c40608f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263994635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2263994635
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3870240644
Short name T512
Test name
Test status
Simulation time 170277908 ps
CPU time 1.11 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:26 PM PDT 24
Peak memory 200268 kb
Host smart-04f903c1-7a40-4f13-81d8-5e3a71136ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870240644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3870240644
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3676712632
Short name T536
Test name
Test status
Simulation time 71651765 ps
CPU time 0.88 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 200072 kb
Host smart-fc40aa15-a16b-402d-a2a2-91154127315d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676712632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3676712632
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3430595224
Short name T468
Test name
Test status
Simulation time 1894385111 ps
CPU time 7.69 seconds
Started Jul 29 05:01:24 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 217360 kb
Host smart-f0820d98-1f47-47c9-8511-28f250bbcfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430595224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3430595224
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3998720840
Short name T167
Test name
Test status
Simulation time 244246596 ps
CPU time 1.01 seconds
Started Jul 29 05:01:31 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 217364 kb
Host smart-753d39c8-cebb-4682-89c3-aa2d04497531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998720840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3998720840
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2754315951
Short name T83
Test name
Test status
Simulation time 197733885 ps
CPU time 0.89 seconds
Started Jul 29 05:01:21 PM PDT 24
Finished Jul 29 05:01:22 PM PDT 24
Peak memory 200060 kb
Host smart-e44654a8-a42a-4f86-bd14-a648dc558fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754315951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2754315951
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2425100042
Short name T492
Test name
Test status
Simulation time 1514924285 ps
CPU time 6.8 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 200488 kb
Host smart-4b357fce-8b82-4cb9-a298-27d70e9f3cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425100042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2425100042
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.12063908
Short name T465
Test name
Test status
Simulation time 141530893 ps
CPU time 1.24 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:26 PM PDT 24
Peak memory 200272 kb
Host smart-ab657f7e-28bb-44c0-89b9-8c60e3e7a39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12063908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.12063908
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1600821482
Short name T224
Test name
Test status
Simulation time 200691396 ps
CPU time 1.48 seconds
Started Jul 29 05:01:24 PM PDT 24
Finished Jul 29 05:01:25 PM PDT 24
Peak memory 200392 kb
Host smart-d067366e-a100-4e9f-aaea-c1b783988f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600821482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1600821482
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2489562897
Short name T56
Test name
Test status
Simulation time 1411581931 ps
CPU time 5.35 seconds
Started Jul 29 05:01:31 PM PDT 24
Finished Jul 29 05:01:37 PM PDT 24
Peak memory 200404 kb
Host smart-212706f3-8457-44b0-810d-15b5aec1f3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489562897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2489562897
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2198994094
Short name T184
Test name
Test status
Simulation time 115703133 ps
CPU time 1.52 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 200040 kb
Host smart-d3fb256b-c584-4f84-b7c2-756ffa96c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198994094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2198994094
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4040188604
Short name T235
Test name
Test status
Simulation time 102275757 ps
CPU time 0.9 seconds
Started Jul 29 05:01:31 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 200160 kb
Host smart-3a9b9de7-8a87-446c-8cec-c2b2a9a82408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040188604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4040188604
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.740713167
Short name T263
Test name
Test status
Simulation time 62904439 ps
CPU time 0.75 seconds
Started Jul 29 05:01:28 PM PDT 24
Finished Jul 29 05:01:29 PM PDT 24
Peak memory 200108 kb
Host smart-1e90b849-7c98-4864-be52-7acdb511c74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740713167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.740713167
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4031369181
Short name T324
Test name
Test status
Simulation time 245078457 ps
CPU time 1.08 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 217356 kb
Host smart-f879bcd1-aff5-48ad-8910-f1dfab9df67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031369181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4031369181
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1508282820
Short name T331
Test name
Test status
Simulation time 148291194 ps
CPU time 0.83 seconds
Started Jul 29 05:01:24 PM PDT 24
Finished Jul 29 05:01:25 PM PDT 24
Peak memory 199972 kb
Host smart-b925e5cb-d423-485c-a7f8-d816ccff6d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508282820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1508282820
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.931333162
Short name T294
Test name
Test status
Simulation time 950492532 ps
CPU time 5.06 seconds
Started Jul 29 05:01:26 PM PDT 24
Finished Jul 29 05:01:31 PM PDT 24
Peak memory 200276 kb
Host smart-103e9caa-0b46-49fd-911c-bf3e7c60fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931333162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.931333162
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.532920323
Short name T276
Test name
Test status
Simulation time 100867325 ps
CPU time 1 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:26 PM PDT 24
Peak memory 200184 kb
Host smart-cf621e66-1126-47e2-a45c-e07c87d33457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532920323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.532920323
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4229959203
Short name T133
Test name
Test status
Simulation time 234205175 ps
CPU time 1.46 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 200344 kb
Host smart-620e9c2f-b8a5-45bc-bc39-02638097e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229959203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4229959203
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1594455115
Short name T240
Test name
Test status
Simulation time 2014171264 ps
CPU time 7.79 seconds
Started Jul 29 05:01:27 PM PDT 24
Finished Jul 29 05:01:34 PM PDT 24
Peak memory 208664 kb
Host smart-40356089-c6aa-4f28-995a-235b1fda8413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594455115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1594455115
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.852649276
Short name T325
Test name
Test status
Simulation time 309582315 ps
CPU time 1.99 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:27 PM PDT 24
Peak memory 208416 kb
Host smart-39739cbf-5684-45e7-9c7b-d24bfd774590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852649276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.852649276
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.263006498
Short name T260
Test name
Test status
Simulation time 144110541 ps
CPU time 1.26 seconds
Started Jul 29 05:01:25 PM PDT 24
Finished Jul 29 05:01:26 PM PDT 24
Peak memory 200292 kb
Host smart-796016f9-dec3-4a8c-80f1-52bab13b97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263006498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.263006498
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4186378500
Short name T423
Test name
Test status
Simulation time 77656397 ps
CPU time 0.81 seconds
Started Jul 29 05:01:32 PM PDT 24
Finished Jul 29 05:01:33 PM PDT 24
Peak memory 200084 kb
Host smart-b77bf79e-308a-49fa-8d4e-141268cdd7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186378500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4186378500
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2457338008
Short name T65
Test name
Test status
Simulation time 1888286482 ps
CPU time 7.3 seconds
Started Jul 29 05:01:31 PM PDT 24
Finished Jul 29 05:01:38 PM PDT 24
Peak memory 221472 kb
Host smart-63a23f70-d04e-49c6-8ed3-b010d6e521f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457338008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2457338008
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1157783868
Short name T92
Test name
Test status
Simulation time 245153563 ps
CPU time 1.09 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:01:31 PM PDT 24
Peak memory 217296 kb
Host smart-2cf94fb7-a99f-4ae1-a39a-2e2ed9b091c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157783868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1157783868
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1766592812
Short name T466
Test name
Test status
Simulation time 151035203 ps
CPU time 0.82 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:01:31 PM PDT 24
Peak memory 200088 kb
Host smart-9ac4e15b-a19b-4c1e-8bbd-c270759d1833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766592812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1766592812
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3808460097
Short name T472
Test name
Test status
Simulation time 835780732 ps
CPU time 4.45 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:01:34 PM PDT 24
Peak memory 200740 kb
Host smart-e8c7ebbe-72d0-43e5-bb43-b900ec274868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808460097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3808460097
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4100741571
Short name T341
Test name
Test status
Simulation time 144402444 ps
CPU time 1.16 seconds
Started Jul 29 05:01:32 PM PDT 24
Finished Jul 29 05:01:33 PM PDT 24
Peak memory 200248 kb
Host smart-e6e5773c-e55a-4408-acf7-eb037637d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100741571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4100741571
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.890606037
Short name T177
Test name
Test status
Simulation time 257693103 ps
CPU time 1.52 seconds
Started Jul 29 05:01:29 PM PDT 24
Finished Jul 29 05:01:31 PM PDT 24
Peak memory 200408 kb
Host smart-b39e3688-afab-4bcb-82f5-652f49f7e3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890606037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.890606037
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2007308359
Short name T345
Test name
Test status
Simulation time 18197891324 ps
CPU time 59.31 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:02:29 PM PDT 24
Peak memory 208732 kb
Host smart-4464ffb1-b130-433e-b495-e63f3cb3b38d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007308359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2007308359
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4271826286
Short name T288
Test name
Test status
Simulation time 119363285 ps
CPU time 1.66 seconds
Started Jul 29 05:01:32 PM PDT 24
Finished Jul 29 05:01:34 PM PDT 24
Peak memory 200048 kb
Host smart-4c4668b5-5d21-4ddf-b72c-48b40c11a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271826286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4271826286
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1073027692
Short name T338
Test name
Test status
Simulation time 72570897 ps
CPU time 0.79 seconds
Started Jul 29 05:02:40 PM PDT 24
Finished Jul 29 05:02:41 PM PDT 24
Peak memory 200284 kb
Host smart-551fdbd1-e5b9-4008-82b9-44da742d6f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073027692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1073027692
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1976285425
Short name T395
Test name
Test status
Simulation time 71818100 ps
CPU time 0.77 seconds
Started Jul 29 05:01:36 PM PDT 24
Finished Jul 29 05:01:37 PM PDT 24
Peak memory 200052 kb
Host smart-e5a50e0b-72c3-4538-afb5-0e0dc900e7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976285425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1976285425
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.734116809
Short name T383
Test name
Test status
Simulation time 1230131793 ps
CPU time 5.68 seconds
Started Jul 29 05:01:37 PM PDT 24
Finished Jul 29 05:01:43 PM PDT 24
Peak memory 217296 kb
Host smart-c0a999c6-989a-4c98-8f1c-37ea4821605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734116809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.734116809
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.278715361
Short name T255
Test name
Test status
Simulation time 244034323 ps
CPU time 1.13 seconds
Started Jul 29 05:01:33 PM PDT 24
Finished Jul 29 05:01:34 PM PDT 24
Peak memory 217516 kb
Host smart-dccb3ff9-a4d0-4092-bc4f-279126246899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278715361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.278715361
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2113916182
Short name T15
Test name
Test status
Simulation time 148648039 ps
CPU time 0.85 seconds
Started Jul 29 05:01:29 PM PDT 24
Finished Jul 29 05:01:30 PM PDT 24
Peak memory 200036 kb
Host smart-81613406-a637-401f-bc5d-217903dc42bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113916182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2113916182
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4246731509
Short name T197
Test name
Test status
Simulation time 1507252049 ps
CPU time 6.25 seconds
Started Jul 29 05:01:32 PM PDT 24
Finished Jul 29 05:01:38 PM PDT 24
Peak memory 200476 kb
Host smart-592a48f3-f8f4-4516-bb57-38061c5dd3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246731509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4246731509
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3812660540
Short name T363
Test name
Test status
Simulation time 99487356 ps
CPU time 0.99 seconds
Started Jul 29 05:01:32 PM PDT 24
Finished Jul 29 05:01:33 PM PDT 24
Peak memory 200268 kb
Host smart-29a0e37d-2a16-46be-9c19-d5c0fb05c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812660540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3812660540
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3843682365
Short name T89
Test name
Test status
Simulation time 128202388 ps
CPU time 1.23 seconds
Started Jul 29 05:01:31 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 200248 kb
Host smart-4226a6ed-a8f8-47dd-baf1-7223119c737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843682365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3843682365
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2355126521
Short name T520
Test name
Test status
Simulation time 9350440506 ps
CPU time 40.11 seconds
Started Jul 29 05:01:33 PM PDT 24
Finished Jul 29 05:02:13 PM PDT 24
Peak memory 200636 kb
Host smart-f93c0e5f-935b-45d0-b965-0510acd5f75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355126521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2355126521
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3705174681
Short name T208
Test name
Test status
Simulation time 127902681 ps
CPU time 1.61 seconds
Started Jul 29 05:01:30 PM PDT 24
Finished Jul 29 05:01:32 PM PDT 24
Peak memory 208656 kb
Host smart-20c74a51-7680-4350-8d89-bc7f2e86e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705174681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3705174681
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2695807424
Short name T424
Test name
Test status
Simulation time 173524513 ps
CPU time 1.15 seconds
Started Jul 29 05:01:32 PM PDT 24
Finished Jul 29 05:01:33 PM PDT 24
Peak memory 200100 kb
Host smart-1c4401e7-69b5-4888-bd35-a2634faee2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695807424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2695807424
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3188614851
Short name T23
Test name
Test status
Simulation time 80282314 ps
CPU time 0.8 seconds
Started Jul 29 05:01:35 PM PDT 24
Finished Jul 29 05:01:35 PM PDT 24
Peak memory 200036 kb
Host smart-64779ba1-2322-45fb-8f1a-da994740191c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188614851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3188614851
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2952873827
Short name T35
Test name
Test status
Simulation time 1909501174 ps
CPU time 7.55 seconds
Started Jul 29 05:01:43 PM PDT 24
Finished Jul 29 05:01:50 PM PDT 24
Peak memory 217632 kb
Host smart-19c554b5-10ad-4c12-8d69-e355f0bf600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952873827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2952873827
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2430775930
Short name T537
Test name
Test status
Simulation time 243571753 ps
CPU time 1.05 seconds
Started Jul 29 05:01:35 PM PDT 24
Finished Jul 29 05:01:36 PM PDT 24
Peak memory 217300 kb
Host smart-0858cb6a-52a4-4cdd-bec9-c7604937b699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430775930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2430775930
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3541836136
Short name T519
Test name
Test status
Simulation time 206280712 ps
CPU time 0.91 seconds
Started Jul 29 05:01:42 PM PDT 24
Finished Jul 29 05:01:43 PM PDT 24
Peak memory 200064 kb
Host smart-ed24e6e1-9d89-43e3-924b-f4420bef0e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541836136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3541836136
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4159676441
Short name T524
Test name
Test status
Simulation time 761461945 ps
CPU time 4.18 seconds
Started Jul 29 05:01:53 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 200368 kb
Host smart-bf80097e-9186-4886-ac50-dd6d7c305121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159676441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4159676441
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3033825596
Short name T432
Test name
Test status
Simulation time 103777175 ps
CPU time 1.01 seconds
Started Jul 29 05:01:43 PM PDT 24
Finished Jul 29 05:01:44 PM PDT 24
Peak memory 200264 kb
Host smart-f2cfb87c-dbd7-41ae-add0-83eb2983ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033825596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3033825596
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3774355982
Short name T528
Test name
Test status
Simulation time 256235673 ps
CPU time 1.48 seconds
Started Jul 29 05:01:36 PM PDT 24
Finished Jul 29 05:01:37 PM PDT 24
Peak memory 200420 kb
Host smart-3728752b-2230-4dac-8da0-5c6cc7b25a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774355982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3774355982
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2088191110
Short name T182
Test name
Test status
Simulation time 5648001495 ps
CPU time 22.26 seconds
Started Jul 29 05:01:43 PM PDT 24
Finished Jul 29 05:02:05 PM PDT 24
Peak memory 200528 kb
Host smart-c7c7a585-63b3-435c-8b85-65def2baa10d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088191110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2088191110
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2762966179
Short name T282
Test name
Test status
Simulation time 269251196 ps
CPU time 1.86 seconds
Started Jul 29 05:01:43 PM PDT 24
Finished Jul 29 05:01:45 PM PDT 24
Peak memory 200216 kb
Host smart-c6f1f39f-eccf-45e7-a8d5-3a2163115bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762966179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2762966179
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.126986074
Short name T493
Test name
Test status
Simulation time 68109441 ps
CPU time 0.76 seconds
Started Jul 29 05:01:35 PM PDT 24
Finished Jul 29 05:01:36 PM PDT 24
Peak memory 200244 kb
Host smart-f68e0673-39de-4f1c-9f84-0679f7dcaaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126986074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.126986074
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2874129872
Short name T541
Test name
Test status
Simulation time 90238519 ps
CPU time 0.86 seconds
Started Jul 29 05:00:10 PM PDT 24
Finished Jul 29 05:00:11 PM PDT 24
Peak memory 199928 kb
Host smart-f70300c6-2ec1-488e-aaa9-2ec7f641ece8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874129872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2874129872
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4146382937
Short name T372
Test name
Test status
Simulation time 2160180424 ps
CPU time 8.36 seconds
Started Jul 29 05:00:13 PM PDT 24
Finished Jul 29 05:00:21 PM PDT 24
Peak memory 221280 kb
Host smart-7f982a95-8b32-4bd3-8a86-aa8e1eae91d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146382937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4146382937
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1363369703
Short name T406
Test name
Test status
Simulation time 243940195 ps
CPU time 1.07 seconds
Started Jul 29 05:00:13 PM PDT 24
Finished Jul 29 05:00:15 PM PDT 24
Peak memory 217396 kb
Host smart-bf547fa6-c1b9-457c-af71-f98087e82ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363369703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1363369703
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4031507156
Short name T474
Test name
Test status
Simulation time 215288809 ps
CPU time 0.93 seconds
Started Jul 29 05:00:09 PM PDT 24
Finished Jul 29 05:00:10 PM PDT 24
Peak memory 199912 kb
Host smart-cb8a6492-d6fc-4fe6-8178-bbd644a7f81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031507156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4031507156
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3577211892
Short name T311
Test name
Test status
Simulation time 1065543501 ps
CPU time 5.37 seconds
Started Jul 29 05:00:05 PM PDT 24
Finished Jul 29 05:00:11 PM PDT 24
Peak memory 200388 kb
Host smart-5464c6fd-92e8-493b-a28c-35c078ccfb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577211892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3577211892
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.47858220
Short name T82
Test name
Test status
Simulation time 8515141455 ps
CPU time 13.65 seconds
Started Jul 29 05:00:12 PM PDT 24
Finished Jul 29 05:00:26 PM PDT 24
Peak memory 217332 kb
Host smart-a74ef20a-3534-418f-a3d3-d2934d079def
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47858220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.47858220
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3657178629
Short name T252
Test name
Test status
Simulation time 98870438 ps
CPU time 1.1 seconds
Started Jul 29 05:00:10 PM PDT 24
Finished Jul 29 05:00:11 PM PDT 24
Peak memory 200172 kb
Host smart-9a13bdab-ea76-4a14-8601-b6086440b1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657178629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3657178629
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4063155897
Short name T270
Test name
Test status
Simulation time 111490618 ps
CPU time 1.26 seconds
Started Jul 29 05:00:06 PM PDT 24
Finished Jul 29 05:00:07 PM PDT 24
Peak memory 200300 kb
Host smart-597fb016-c094-4235-9098-0d88df6b4582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063155897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4063155897
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2137825983
Short name T43
Test name
Test status
Simulation time 2828506613 ps
CPU time 12.04 seconds
Started Jul 29 05:00:14 PM PDT 24
Finished Jul 29 05:00:26 PM PDT 24
Peak memory 200392 kb
Host smart-9b6b6c1a-14e7-441b-b589-abf744e61bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137825983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2137825983
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2562927326
Short name T148
Test name
Test status
Simulation time 341401964 ps
CPU time 2.25 seconds
Started Jul 29 05:00:12 PM PDT 24
Finished Jul 29 05:00:14 PM PDT 24
Peak memory 200124 kb
Host smart-ba3b3d21-27af-445b-8f3e-6782869c5e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562927326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2562927326
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.196223777
Short name T253
Test name
Test status
Simulation time 62365935 ps
CPU time 0.72 seconds
Started Jul 29 05:00:11 PM PDT 24
Finished Jul 29 05:00:12 PM PDT 24
Peak memory 200152 kb
Host smart-c12d960f-b0ae-45c0-ba70-3d4dd0b6cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196223777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.196223777
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.142648470
Short name T397
Test name
Test status
Simulation time 56495292 ps
CPU time 0.84 seconds
Started Jul 29 05:01:45 PM PDT 24
Finished Jul 29 05:01:46 PM PDT 24
Peak memory 200012 kb
Host smart-7fae0cc0-c776-429c-97e3-f091ac3a4ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142648470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.142648470
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1645879806
Short name T365
Test name
Test status
Simulation time 1215589292 ps
CPU time 5.75 seconds
Started Jul 29 05:01:46 PM PDT 24
Finished Jul 29 05:01:52 PM PDT 24
Peak memory 217544 kb
Host smart-c4d3b0e0-f5f0-48e9-9ed4-33ce426d474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645879806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1645879806
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1240318132
Short name T444
Test name
Test status
Simulation time 244163356 ps
CPU time 1.07 seconds
Started Jul 29 05:01:47 PM PDT 24
Finished Jul 29 05:01:48 PM PDT 24
Peak memory 217432 kb
Host smart-c5f95d88-800b-443b-96b1-e71c99096300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240318132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1240318132
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1433417715
Short name T515
Test name
Test status
Simulation time 199532561 ps
CPU time 0.88 seconds
Started Jul 29 05:01:41 PM PDT 24
Finished Jul 29 05:01:42 PM PDT 24
Peak memory 199960 kb
Host smart-5cc64a5f-6f94-445c-b34b-0ef7ebad3ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433417715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1433417715
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1011237508
Short name T220
Test name
Test status
Simulation time 1166954941 ps
CPU time 4.83 seconds
Started Jul 29 05:01:42 PM PDT 24
Finished Jul 29 05:01:46 PM PDT 24
Peak memory 200516 kb
Host smart-27eaaa18-9e68-47f0-acc8-66639184f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011237508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1011237508
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.156090198
Short name T181
Test name
Test status
Simulation time 155154508 ps
CPU time 1.2 seconds
Started Jul 29 05:01:40 PM PDT 24
Finished Jul 29 05:01:42 PM PDT 24
Peak memory 200280 kb
Host smart-ffd4b5d6-198c-4f61-bb0c-20165b36e77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156090198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.156090198
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3655784901
Short name T535
Test name
Test status
Simulation time 123118129 ps
CPU time 1.21 seconds
Started Jul 29 05:01:40 PM PDT 24
Finished Jul 29 05:01:41 PM PDT 24
Peak memory 200412 kb
Host smart-d7b2c8ed-910f-470f-86b7-13a7de0bbb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655784901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3655784901
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.135281118
Short name T442
Test name
Test status
Simulation time 1523217914 ps
CPU time 7.39 seconds
Started Jul 29 05:01:46 PM PDT 24
Finished Jul 29 05:01:53 PM PDT 24
Peak memory 200292 kb
Host smart-4c3fedd1-0bdb-4ce2-98d3-7b07e88d865b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135281118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.135281118
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3142204095
Short name T321
Test name
Test status
Simulation time 328490275 ps
CPU time 2.2 seconds
Started Jul 29 05:01:42 PM PDT 24
Finished Jul 29 05:01:44 PM PDT 24
Peak memory 200200 kb
Host smart-76395775-e255-40f3-b15e-eaf7093f24db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142204095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3142204095
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1991551641
Short name T483
Test name
Test status
Simulation time 139578395 ps
CPU time 1.11 seconds
Started Jul 29 05:01:39 PM PDT 24
Finished Jul 29 05:01:41 PM PDT 24
Peak memory 200272 kb
Host smart-2054432f-6b4d-40e5-8eb0-c199252324db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991551641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1991551641
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1898577410
Short name T169
Test name
Test status
Simulation time 75031474 ps
CPU time 0.79 seconds
Started Jul 29 05:01:44 PM PDT 24
Finished Jul 29 05:01:45 PM PDT 24
Peak memory 200308 kb
Host smart-84cac806-27d5-43d5-bdf7-c71ff6f6f5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898577410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1898577410
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2905502835
Short name T50
Test name
Test status
Simulation time 1230545591 ps
CPU time 6.04 seconds
Started Jul 29 05:01:45 PM PDT 24
Finished Jul 29 05:01:52 PM PDT 24
Peak memory 217576 kb
Host smart-afbd8cbb-aa55-4228-96f7-3ea1ef955bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905502835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2905502835
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3324198536
Short name T292
Test name
Test status
Simulation time 243611604 ps
CPU time 1.05 seconds
Started Jul 29 05:01:45 PM PDT 24
Finished Jul 29 05:01:46 PM PDT 24
Peak memory 217312 kb
Host smart-99823097-3c81-4a5c-88a4-709a3aa57734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324198536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3324198536
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1136799903
Short name T20
Test name
Test status
Simulation time 131279643 ps
CPU time 0.76 seconds
Started Jul 29 05:01:50 PM PDT 24
Finished Jul 29 05:01:50 PM PDT 24
Peak memory 200044 kb
Host smart-34322e4e-fc8e-4d64-a5c6-8696a1ead196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136799903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1136799903
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2193740455
Short name T454
Test name
Test status
Simulation time 1242839707 ps
CPU time 5.72 seconds
Started Jul 29 05:01:46 PM PDT 24
Finished Jul 29 05:01:52 PM PDT 24
Peak memory 200356 kb
Host smart-4dcf87fc-485a-413f-b87c-c4d09767c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193740455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2193740455
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.84614725
Short name T144
Test name
Test status
Simulation time 182527349 ps
CPU time 1.2 seconds
Started Jul 29 05:01:44 PM PDT 24
Finished Jul 29 05:01:46 PM PDT 24
Peak memory 200256 kb
Host smart-828c4649-1b31-4246-91b3-fcc3dece2f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84614725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.84614725
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.4261050576
Short name T336
Test name
Test status
Simulation time 115524177 ps
CPU time 1.09 seconds
Started Jul 29 05:01:47 PM PDT 24
Finished Jul 29 05:01:49 PM PDT 24
Peak memory 200376 kb
Host smart-f9a09fbc-d27b-4c7a-833e-193c1ad67401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261050576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4261050576
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.410029629
Short name T87
Test name
Test status
Simulation time 13693177209 ps
CPU time 48.42 seconds
Started Jul 29 05:01:46 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 200376 kb
Host smart-889e20a5-3a94-4c8d-878b-2f4943db2591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410029629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.410029629
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2008515143
Short name T201
Test name
Test status
Simulation time 390654813 ps
CPU time 2.21 seconds
Started Jul 29 05:01:45 PM PDT 24
Finished Jul 29 05:01:47 PM PDT 24
Peak memory 200200 kb
Host smart-5ca2116f-9a49-4e11-bf01-facb06ae8d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008515143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2008515143
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3375904766
Short name T315
Test name
Test status
Simulation time 95706996 ps
CPU time 0.92 seconds
Started Jul 29 05:01:44 PM PDT 24
Finished Jul 29 05:01:45 PM PDT 24
Peak memory 200224 kb
Host smart-01bb7799-10e7-4ef0-b0dd-221ccf40f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375904766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3375904766
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2095603836
Short name T78
Test name
Test status
Simulation time 76864574 ps
CPU time 0.87 seconds
Started Jul 29 05:01:58 PM PDT 24
Finished Jul 29 05:01:59 PM PDT 24
Peak memory 200044 kb
Host smart-eb8505d8-f506-45e7-b1c4-303503e88180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095603836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2095603836
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3417430778
Short name T418
Test name
Test status
Simulation time 1892037123 ps
CPU time 7.78 seconds
Started Jul 29 05:01:51 PM PDT 24
Finished Jul 29 05:02:00 PM PDT 24
Peak memory 216708 kb
Host smart-9ae15080-bc10-46c6-8bad-c617672a3c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417430778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3417430778
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3658895817
Short name T400
Test name
Test status
Simulation time 244111592 ps
CPU time 1.05 seconds
Started Jul 29 05:01:50 PM PDT 24
Finished Jul 29 05:01:52 PM PDT 24
Peak memory 217316 kb
Host smart-f2d2f7a8-a48e-4786-add0-546228db9f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658895817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3658895817
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1599382616
Short name T358
Test name
Test status
Simulation time 150743189 ps
CPU time 0.85 seconds
Started Jul 29 05:01:51 PM PDT 24
Finished Jul 29 05:01:52 PM PDT 24
Peak memory 199980 kb
Host smart-7c31e141-7127-48f4-a555-39fc921725cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599382616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1599382616
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1916078409
Short name T272
Test name
Test status
Simulation time 1945422157 ps
CPU time 7.2 seconds
Started Jul 29 05:01:51 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 200524 kb
Host smart-0841badc-0840-48c7-b9ff-db0be0d2f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916078409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1916078409
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3322658393
Short name T85
Test name
Test status
Simulation time 159749131 ps
CPU time 1.14 seconds
Started Jul 29 05:01:52 PM PDT 24
Finished Jul 29 05:01:54 PM PDT 24
Peak memory 200272 kb
Host smart-64593e66-0f00-4d74-b8b7-a6e3aa985ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322658393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3322658393
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2280354772
Short name T380
Test name
Test status
Simulation time 201497351 ps
CPU time 1.36 seconds
Started Jul 29 05:01:50 PM PDT 24
Finished Jul 29 05:01:52 PM PDT 24
Peak memory 200516 kb
Host smart-a1bb58ca-cca0-45cf-98a8-3fb582190801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280354772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2280354772
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.752795501
Short name T369
Test name
Test status
Simulation time 1884097470 ps
CPU time 8.67 seconds
Started Jul 29 05:01:49 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 200344 kb
Host smart-c756f03d-6293-43a3-955b-82693698254d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752795501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.752795501
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.4153658923
Short name T61
Test name
Test status
Simulation time 111151305 ps
CPU time 1.48 seconds
Started Jul 29 05:01:51 PM PDT 24
Finished Jul 29 05:01:53 PM PDT 24
Peak memory 200104 kb
Host smart-600563ea-a177-4642-b1fc-485c815b4850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153658923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4153658923
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.34531581
Short name T137
Test name
Test status
Simulation time 142242337 ps
CPU time 1.07 seconds
Started Jul 29 05:01:51 PM PDT 24
Finished Jul 29 05:01:53 PM PDT 24
Peak memory 200208 kb
Host smart-a02a9a07-7597-430b-a4db-aae565e0396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34531581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.34531581
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3950666008
Short name T84
Test name
Test status
Simulation time 76872707 ps
CPU time 0.83 seconds
Started Jul 29 05:01:56 PM PDT 24
Finished Jul 29 05:01:57 PM PDT 24
Peak memory 199972 kb
Host smart-11287321-3150-42be-8609-b8582da93011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950666008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3950666008
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1637532762
Short name T322
Test name
Test status
Simulation time 2364584738 ps
CPU time 7.99 seconds
Started Jul 29 05:01:57 PM PDT 24
Finished Jul 29 05:02:05 PM PDT 24
Peak memory 217692 kb
Host smart-1213ec80-119d-476c-86da-687d13ade2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637532762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1637532762
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4149828669
Short name T377
Test name
Test status
Simulation time 244278666 ps
CPU time 1.1 seconds
Started Jul 29 05:01:58 PM PDT 24
Finished Jul 29 05:02:00 PM PDT 24
Peak memory 217444 kb
Host smart-fcca8931-640d-4fee-8f86-d20123124802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149828669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4149828669
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3851278953
Short name T16
Test name
Test status
Simulation time 209038627 ps
CPU time 0.96 seconds
Started Jul 29 05:01:57 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 200012 kb
Host smart-6157c1ce-b53c-4a84-8beb-a57afe2614a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851278953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3851278953
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.222778648
Short name T55
Test name
Test status
Simulation time 1593880658 ps
CPU time 7.33 seconds
Started Jul 29 05:01:59 PM PDT 24
Finished Jul 29 05:02:06 PM PDT 24
Peak memory 200468 kb
Host smart-071d65c9-9ecd-4211-886a-9cb762c01986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222778648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.222778648
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2976832525
Short name T484
Test name
Test status
Simulation time 185704235 ps
CPU time 1.29 seconds
Started Jul 29 05:01:56 PM PDT 24
Finished Jul 29 05:01:57 PM PDT 24
Peak memory 200144 kb
Host smart-3a628534-20aa-48b4-8899-c01e409cd762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976832525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2976832525
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1184054012
Short name T297
Test name
Test status
Simulation time 129285090 ps
CPU time 1.24 seconds
Started Jul 29 05:01:57 PM PDT 24
Finished Jul 29 05:01:58 PM PDT 24
Peak memory 200628 kb
Host smart-2c688432-6141-45ee-92e5-c68e56186361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184054012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1184054012
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2198700011
Short name T237
Test name
Test status
Simulation time 358483935 ps
CPU time 2.53 seconds
Started Jul 29 05:01:56 PM PDT 24
Finished Jul 29 05:01:59 PM PDT 24
Peak memory 200128 kb
Host smart-8ab1f59e-c1aa-47d3-a581-97d176c99038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198700011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2198700011
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3692927952
Short name T361
Test name
Test status
Simulation time 162697644 ps
CPU time 1.14 seconds
Started Jul 29 05:01:58 PM PDT 24
Finished Jul 29 05:01:59 PM PDT 24
Peak memory 200332 kb
Host smart-fb02c86d-b2e0-4d2b-a04f-aa39fcc5eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692927952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3692927952
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.4185249296
Short name T491
Test name
Test status
Simulation time 69820359 ps
CPU time 0.82 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:05 PM PDT 24
Peak memory 199908 kb
Host smart-df140694-6078-4155-abdd-9f3b7ceb0575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185249296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4185249296
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3990474974
Short name T495
Test name
Test status
Simulation time 2328388331 ps
CPU time 8.68 seconds
Started Jul 29 05:02:06 PM PDT 24
Finished Jul 29 05:02:15 PM PDT 24
Peak memory 217716 kb
Host smart-ba76f5d9-e132-40d2-8815-f8ba77478c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990474974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3990474974
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4249674727
Short name T257
Test name
Test status
Simulation time 244241206 ps
CPU time 1.06 seconds
Started Jul 29 05:02:07 PM PDT 24
Finished Jul 29 05:02:08 PM PDT 24
Peak memory 217396 kb
Host smart-82dc7666-76c9-495b-87f6-3cd7bbdc1a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249674727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4249674727
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.658288989
Short name T471
Test name
Test status
Simulation time 131567625 ps
CPU time 0.79 seconds
Started Jul 29 05:02:00 PM PDT 24
Finished Jul 29 05:02:00 PM PDT 24
Peak memory 200072 kb
Host smart-e84fcfd5-9807-47ac-a575-1408172b843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658288989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.658288989
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2867627675
Short name T473
Test name
Test status
Simulation time 1369584563 ps
CPU time 5.7 seconds
Started Jul 29 05:01:57 PM PDT 24
Finished Jul 29 05:02:03 PM PDT 24
Peak memory 200376 kb
Host smart-81ed3bfb-378d-4c21-aed2-e5d40125fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867627675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2867627675
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2045704833
Short name T166
Test name
Test status
Simulation time 109445644 ps
CPU time 1.01 seconds
Started Jul 29 05:02:06 PM PDT 24
Finished Jul 29 05:02:07 PM PDT 24
Peak memory 200236 kb
Host smart-9c65802a-fa25-4f37-8eb3-c78883895696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045704833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2045704833
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2123959525
Short name T203
Test name
Test status
Simulation time 125192828 ps
CPU time 1.31 seconds
Started Jul 29 05:01:59 PM PDT 24
Finished Jul 29 05:02:00 PM PDT 24
Peak memory 200296 kb
Host smart-3b79fc97-3abc-4082-95f5-4830b5cf238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123959525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2123959525
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3755786831
Short name T475
Test name
Test status
Simulation time 2122886431 ps
CPU time 8.08 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:12 PM PDT 24
Peak memory 200460 kb
Host smart-c6a2adb2-8a2d-4e44-9c03-2120a138a00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755786831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3755786831
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4128778050
Short name T485
Test name
Test status
Simulation time 395876826 ps
CPU time 2.29 seconds
Started Jul 29 05:02:02 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 200080 kb
Host smart-4fb0453e-5d77-47e0-aed1-0f12e33d4cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128778050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4128778050
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1239323743
Short name T328
Test name
Test status
Simulation time 139778839 ps
CPU time 1.23 seconds
Started Jul 29 05:02:02 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 200280 kb
Host smart-78b13874-6a82-45f8-aeb4-ebaa29433050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239323743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1239323743
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.960238507
Short name T308
Test name
Test status
Simulation time 61581119 ps
CPU time 0.74 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:05 PM PDT 24
Peak memory 199960 kb
Host smart-5df1be40-67f4-43ea-a0f4-f55193b0b9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960238507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.960238507
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1336558474
Short name T28
Test name
Test status
Simulation time 1885370636 ps
CPU time 7.6 seconds
Started Jul 29 05:02:06 PM PDT 24
Finished Jul 29 05:02:14 PM PDT 24
Peak memory 221588 kb
Host smart-bd30a22b-ed6e-4e93-900e-bc9eb9e2533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336558474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1336558474
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4209407407
Short name T355
Test name
Test status
Simulation time 246197568 ps
CPU time 1.12 seconds
Started Jul 29 05:02:03 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 217404 kb
Host smart-4b3568ac-8a40-4dd5-abbd-a25c3a94d430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209407407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4209407407
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4253746802
Short name T239
Test name
Test status
Simulation time 150526374 ps
CPU time 0.89 seconds
Started Jul 29 05:02:03 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 200060 kb
Host smart-25854c0b-e075-46f8-bc46-ea41d7e6481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253746802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4253746802
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1139965727
Short name T280
Test name
Test status
Simulation time 1116632034 ps
CPU time 4.69 seconds
Started Jul 29 05:02:08 PM PDT 24
Finished Jul 29 05:02:13 PM PDT 24
Peak memory 200424 kb
Host smart-8a1abdff-054b-4d3b-9767-81891b00fee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139965727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1139965727
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1216453013
Short name T146
Test name
Test status
Simulation time 146366615 ps
CPU time 1.15 seconds
Started Jul 29 05:02:06 PM PDT 24
Finished Jul 29 05:02:07 PM PDT 24
Peak memory 200148 kb
Host smart-fd239f54-061d-4dd2-8d4a-6db94d229b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216453013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1216453013
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3906083676
Short name T138
Test name
Test status
Simulation time 121699690 ps
CPU time 1.2 seconds
Started Jul 29 05:02:03 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 200320 kb
Host smart-9909582f-4a28-42b6-8624-309996c6f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906083676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3906083676
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2518526953
Short name T25
Test name
Test status
Simulation time 4612780214 ps
CPU time 15.59 seconds
Started Jul 29 05:02:03 PM PDT 24
Finished Jul 29 05:02:19 PM PDT 24
Peak memory 208584 kb
Host smart-3db53150-4120-4804-9fdc-7b3269cdef9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518526953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2518526953
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2128374711
Short name T283
Test name
Test status
Simulation time 354699193 ps
CPU time 2.2 seconds
Started Jul 29 05:02:07 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 200160 kb
Host smart-b0129a04-1022-4d57-a482-702a44a82325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128374711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2128374711
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1774028999
Short name T407
Test name
Test status
Simulation time 114116507 ps
CPU time 1.03 seconds
Started Jul 29 05:02:03 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 200200 kb
Host smart-84a10371-b464-4207-8da6-ed93eea15afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774028999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1774028999
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.477097359
Short name T469
Test name
Test status
Simulation time 71075685 ps
CPU time 0.76 seconds
Started Jul 29 05:02:17 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 200080 kb
Host smart-56de82d2-5728-43b4-b46c-bca0afa77215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477097359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.477097359
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.279096467
Short name T42
Test name
Test status
Simulation time 1886007385 ps
CPU time 7.2 seconds
Started Jul 29 05:02:07 PM PDT 24
Finished Jul 29 05:02:14 PM PDT 24
Peak memory 229768 kb
Host smart-75777989-5c96-4eb7-8181-2345ebf2db26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279096467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.279096467
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3210560659
Short name T538
Test name
Test status
Simulation time 245289189 ps
CPU time 1.06 seconds
Started Jul 29 05:02:07 PM PDT 24
Finished Jul 29 05:02:08 PM PDT 24
Peak memory 217508 kb
Host smart-200140c7-3772-4cbf-8782-681076b2b243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210560659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3210560659
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1055076303
Short name T213
Test name
Test status
Simulation time 229193042 ps
CPU time 0.93 seconds
Started Jul 29 05:02:05 PM PDT 24
Finished Jul 29 05:02:06 PM PDT 24
Peak memory 199972 kb
Host smart-d61f5a7c-8d2c-4dea-bf80-2a82547d367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055076303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1055076303
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3804236664
Short name T376
Test name
Test status
Simulation time 826123255 ps
CPU time 3.95 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:09 PM PDT 24
Peak memory 200420 kb
Host smart-821fc29a-6839-4eee-a2be-ff9126af8994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804236664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3804236664
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2729429488
Short name T261
Test name
Test status
Simulation time 145364461 ps
CPU time 1.17 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:05 PM PDT 24
Peak memory 200172 kb
Host smart-7bf74244-24f7-4740-98b0-c1d11c578d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729429488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2729429488
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.125469312
Short name T301
Test name
Test status
Simulation time 124703979 ps
CPU time 1.32 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:06 PM PDT 24
Peak memory 200388 kb
Host smart-312f3990-0704-4ad5-98a3-6757487250c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125469312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.125469312
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3763480680
Short name T234
Test name
Test status
Simulation time 2688129786 ps
CPU time 10.52 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:20 PM PDT 24
Peak memory 200536 kb
Host smart-0d852163-9576-4df3-80bc-931a8fb11d31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763480680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3763480680
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.883571506
Short name T293
Test name
Test status
Simulation time 452542832 ps
CPU time 2.64 seconds
Started Jul 29 05:02:04 PM PDT 24
Finished Jul 29 05:02:07 PM PDT 24
Peak memory 200216 kb
Host smart-c095beb0-ee78-42ff-8188-574560bd7dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883571506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.883571506
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3511421871
Short name T494
Test name
Test status
Simulation time 89952786 ps
CPU time 0.96 seconds
Started Jul 29 05:02:03 PM PDT 24
Finished Jul 29 05:02:04 PM PDT 24
Peak memory 200268 kb
Host smart-0b06c8d5-011f-44a0-99a4-9342b260f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511421871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3511421871
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2912946728
Short name T298
Test name
Test status
Simulation time 59481826 ps
CPU time 0.75 seconds
Started Jul 29 05:02:11 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 200044 kb
Host smart-4e57fc68-b815-4606-aeac-7f29a1f51763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912946728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2912946728
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3281954067
Short name T402
Test name
Test status
Simulation time 2352930175 ps
CPU time 8.23 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:24 PM PDT 24
Peak memory 221044 kb
Host smart-d2a5ae07-bc34-411b-96de-1d53b367876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281954067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3281954067
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1366457757
Short name T379
Test name
Test status
Simulation time 244529194 ps
CPU time 1.07 seconds
Started Jul 29 05:02:17 PM PDT 24
Finished Jul 29 05:02:18 PM PDT 24
Peak memory 217384 kb
Host smart-c5e5d64a-f86d-494e-a4a5-0ab737afe01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366457757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1366457757
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.4202569501
Short name T18
Test name
Test status
Simulation time 192609602 ps
CPU time 0.87 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 200088 kb
Host smart-38e17cbd-8be9-437a-9e68-e5e4c0138f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202569501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4202569501
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.385102734
Short name T508
Test name
Test status
Simulation time 902365632 ps
CPU time 4.49 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:21 PM PDT 24
Peak memory 200412 kb
Host smart-b5c3c33d-9348-4c88-9d3f-42dedcab7101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385102734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.385102734
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1430378159
Short name T189
Test name
Test status
Simulation time 113106357 ps
CPU time 0.97 seconds
Started Jul 29 05:02:13 PM PDT 24
Finished Jul 29 05:02:14 PM PDT 24
Peak memory 200268 kb
Host smart-d5276416-d103-4778-a7ac-1cb3a985f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430378159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1430378159
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.719066047
Short name T405
Test name
Test status
Simulation time 254647845 ps
CPU time 1.63 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 200416 kb
Host smart-905fedce-ab23-4965-b7db-60de178ebd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719066047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.719066047
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1854158555
Short name T450
Test name
Test status
Simulation time 7368498006 ps
CPU time 30.07 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:40 PM PDT 24
Peak memory 208744 kb
Host smart-2c798d6a-05cc-451d-b724-ad77d5b809b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854158555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1854158555
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1824994324
Short name T202
Test name
Test status
Simulation time 466950542 ps
CPU time 2.63 seconds
Started Jul 29 05:02:11 PM PDT 24
Finished Jul 29 05:02:13 PM PDT 24
Peak memory 200188 kb
Host smart-f5ec07ce-159c-4749-a976-4136fc527068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824994324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1824994324
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3473151993
Short name T58
Test name
Test status
Simulation time 69788195 ps
CPU time 0.78 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 200268 kb
Host smart-2099194b-d410-43c7-a7c7-e559fb3629e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473151993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3473151993
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3559527287
Short name T140
Test name
Test status
Simulation time 80242176 ps
CPU time 0.8 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:16 PM PDT 24
Peak memory 200084 kb
Host smart-2e4f94ff-59af-4919-8c3f-2602e9aa0d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559527287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3559527287
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3210181756
Short name T47
Test name
Test status
Simulation time 1238506819 ps
CPU time 5.79 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:22 PM PDT 24
Peak memory 217692 kb
Host smart-0ced009a-21c6-4abf-a008-c70aebdc460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210181756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3210181756
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.879802010
Short name T439
Test name
Test status
Simulation time 244167662 ps
CPU time 1.05 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:18 PM PDT 24
Peak memory 217384 kb
Host smart-54ad3447-aa46-4b06-8133-99aeec42e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879802010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.879802010
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3188999547
Short name T327
Test name
Test status
Simulation time 115524218 ps
CPU time 0.79 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:15 PM PDT 24
Peak memory 200072 kb
Host smart-b2e2b83e-0978-40ce-a45f-e9519fb974bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188999547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3188999547
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1273876468
Short name T370
Test name
Test status
Simulation time 1061909534 ps
CPU time 4.63 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:15 PM PDT 24
Peak memory 200440 kb
Host smart-e8b8c8f3-e27c-4457-81ee-c8df1742efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273876468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1273876468
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3915892593
Short name T513
Test name
Test status
Simulation time 108689084 ps
CPU time 1.09 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 200176 kb
Host smart-c7bc632a-d2c1-4bdf-898b-709bdb59c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915892593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3915892593
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4201822290
Short name T391
Test name
Test status
Simulation time 216577847 ps
CPU time 1.45 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:18 PM PDT 24
Peak memory 200452 kb
Host smart-e5a59ff6-1dfd-4a4b-9799-f3a6047d9c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201822290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4201822290
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3747180417
Short name T129
Test name
Test status
Simulation time 2182459790 ps
CPU time 7.6 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:22 PM PDT 24
Peak memory 200532 kb
Host smart-9275d2ed-07d2-43f7-a780-ff3e40ddd56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747180417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3747180417
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.864932330
Short name T510
Test name
Test status
Simulation time 157748217 ps
CPU time 1.9 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 200220 kb
Host smart-ba3bd009-4262-488f-ab53-15fc9a144bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864932330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.864932330
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2371605430
Short name T225
Test name
Test status
Simulation time 69161900 ps
CPU time 0.77 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 200264 kb
Host smart-07d47c0d-9f6d-4a2e-94a8-aadde2b8b9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371605430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2371605430
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.857310311
Short name T271
Test name
Test status
Simulation time 67155037 ps
CPU time 0.74 seconds
Started Jul 29 05:02:19 PM PDT 24
Finished Jul 29 05:02:20 PM PDT 24
Peak memory 200144 kb
Host smart-7466e731-3879-42e1-bea3-cf3be53ea814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857310311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.857310311
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4034379511
Short name T64
Test name
Test status
Simulation time 1212744368 ps
CPU time 6.04 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:16 PM PDT 24
Peak memory 216848 kb
Host smart-481775ed-8e36-40fc-96cf-f2c9a867a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034379511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4034379511
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2752370103
Short name T215
Test name
Test status
Simulation time 245319359 ps
CPU time 1.07 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 217448 kb
Host smart-b9de9ec1-f284-48a6-8e0a-2ead5a191954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752370103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2752370103
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.348885659
Short name T482
Test name
Test status
Simulation time 148026141 ps
CPU time 0.82 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:10 PM PDT 24
Peak memory 200004 kb
Host smart-29b92d32-4805-4031-8fe7-23b43daa1904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348885659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.348885659
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.663015613
Short name T131
Test name
Test status
Simulation time 1964888124 ps
CPU time 7.38 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 200424 kb
Host smart-f520c8e5-0273-495f-bfb9-07d23eeb3955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663015613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.663015613
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2090091797
Short name T194
Test name
Test status
Simulation time 106322788 ps
CPU time 1 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 200280 kb
Host smart-c060bf6d-9527-462e-ab60-3628fd090783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090091797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2090091797
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1861906911
Short name T168
Test name
Test status
Simulation time 266112409 ps
CPU time 1.51 seconds
Started Jul 29 05:02:10 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 200352 kb
Host smart-e6d315f0-771b-4a60-8f64-4a4e011e76b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861906911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1861906911
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.530310136
Short name T57
Test name
Test status
Simulation time 113940378 ps
CPU time 1.44 seconds
Started Jul 29 05:02:09 PM PDT 24
Finished Jul 29 05:02:11 PM PDT 24
Peak memory 200216 kb
Host smart-29451a4c-8cf0-4504-b311-de4cf0cba1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530310136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.530310136
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3529292063
Short name T242
Test name
Test status
Simulation time 213567808 ps
CPU time 1.35 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:18 PM PDT 24
Peak memory 200204 kb
Host smart-0f5be29a-6102-457b-b708-3c5751da34f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529292063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3529292063
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1738186280
Short name T486
Test name
Test status
Simulation time 72949373 ps
CPU time 0.81 seconds
Started Jul 29 05:00:21 PM PDT 24
Finished Jul 29 05:00:22 PM PDT 24
Peak memory 199988 kb
Host smart-84ba2397-afea-4748-ba94-9c8ad7edbc9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738186280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1738186280
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2412222611
Short name T386
Test name
Test status
Simulation time 1227831498 ps
CPU time 6.11 seconds
Started Jul 29 05:00:15 PM PDT 24
Finished Jul 29 05:00:22 PM PDT 24
Peak memory 217476 kb
Host smart-3a75f457-4e2c-46f7-adf2-2d3329b6f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412222611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2412222611
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2259921823
Short name T152
Test name
Test status
Simulation time 244068725 ps
CPU time 1.09 seconds
Started Jul 29 05:00:17 PM PDT 24
Finished Jul 29 05:00:18 PM PDT 24
Peak memory 217332 kb
Host smart-3f724b9e-0eea-4ada-b0db-e0d85817b8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259921823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2259921823
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.701643442
Short name T14
Test name
Test status
Simulation time 135397078 ps
CPU time 0.84 seconds
Started Jul 29 05:00:20 PM PDT 24
Finished Jul 29 05:00:21 PM PDT 24
Peak memory 199912 kb
Host smart-419036a5-6d76-4e35-844e-32c5afec513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701643442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.701643442
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2817602456
Short name T498
Test name
Test status
Simulation time 883122234 ps
CPU time 5.15 seconds
Started Jul 29 05:00:20 PM PDT 24
Finished Jul 29 05:00:25 PM PDT 24
Peak memory 200392 kb
Host smart-ef445b1b-7773-469b-a2b9-b8f0b2be85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817602456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2817602456
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3010147463
Short name T76
Test name
Test status
Simulation time 8291355931 ps
CPU time 16.35 seconds
Started Jul 29 05:00:16 PM PDT 24
Finished Jul 29 05:00:32 PM PDT 24
Peak memory 217036 kb
Host smart-61f6429c-022b-45e6-bd43-f2ced1d13022
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010147463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3010147463
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2663316088
Short name T348
Test name
Test status
Simulation time 106525798 ps
CPU time 1 seconds
Started Jul 29 05:00:17 PM PDT 24
Finished Jul 29 05:00:18 PM PDT 24
Peak memory 200096 kb
Host smart-68330fed-7a66-420e-b48d-d8c26a833c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663316088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2663316088
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.214130697
Short name T422
Test name
Test status
Simulation time 254917769 ps
CPU time 1.75 seconds
Started Jul 29 05:00:21 PM PDT 24
Finished Jul 29 05:00:23 PM PDT 24
Peak memory 200280 kb
Host smart-18bc18ab-6467-450f-885b-8e0b3fd16767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214130697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.214130697
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.330855164
Short name T477
Test name
Test status
Simulation time 4572947184 ps
CPU time 21.58 seconds
Started Jul 29 05:00:22 PM PDT 24
Finished Jul 29 05:00:44 PM PDT 24
Peak memory 200428 kb
Host smart-dc4de0c6-903e-4e30-a1c4-a3d417183fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330855164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.330855164
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2105498507
Short name T141
Test name
Test status
Simulation time 266692367 ps
CPU time 1.91 seconds
Started Jul 29 05:00:21 PM PDT 24
Finished Jul 29 05:00:23 PM PDT 24
Peak memory 200216 kb
Host smart-419b0207-ac98-4bd0-a6de-839e7520f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105498507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2105498507
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3900716118
Short name T304
Test name
Test status
Simulation time 85945913 ps
CPU time 0.88 seconds
Started Jul 29 05:00:17 PM PDT 24
Finished Jul 29 05:00:18 PM PDT 24
Peak memory 200272 kb
Host smart-e14b8d9d-8d47-4888-80f1-926d8c1cb5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900716118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3900716118
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1585805557
Short name T457
Test name
Test status
Simulation time 84026776 ps
CPU time 0.84 seconds
Started Jul 29 05:02:16 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 200036 kb
Host smart-fc6ac6fd-b0a0-482c-a0c9-3b976e6cd2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585805557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1585805557
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1523636712
Short name T48
Test name
Test status
Simulation time 1879006359 ps
CPU time 7.78 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:22 PM PDT 24
Peak memory 217676 kb
Host smart-f8def8fe-3f81-424f-a119-6cfeb64290b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523636712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1523636712
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2033682182
Short name T458
Test name
Test status
Simulation time 245232593 ps
CPU time 1.1 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 217340 kb
Host smart-cba89274-584c-4053-9354-ffcb7832a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033682182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2033682182
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2260613185
Short name T446
Test name
Test status
Simulation time 133621849 ps
CPU time 0.83 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:15 PM PDT 24
Peak memory 200072 kb
Host smart-52e27d48-b820-4045-b750-aa0aede57607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260613185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2260613185
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1767659929
Short name T226
Test name
Test status
Simulation time 1406457455 ps
CPU time 5.55 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:20 PM PDT 24
Peak memory 200360 kb
Host smart-5c56708e-8eff-48bf-833d-4b5eb9569e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767659929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1767659929
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1945162137
Short name T136
Test name
Test status
Simulation time 181903403 ps
CPU time 1.19 seconds
Started Jul 29 05:02:17 PM PDT 24
Finished Jul 29 05:02:18 PM PDT 24
Peak memory 200016 kb
Host smart-e934defc-e693-4ace-a3fd-e55d6ecdb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945162137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1945162137
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.867739859
Short name T199
Test name
Test status
Simulation time 265458503 ps
CPU time 1.58 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:16 PM PDT 24
Peak memory 200392 kb
Host smart-56577864-20d9-464f-b5b0-dd3ce4bda2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867739859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.867739859
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2168060512
Short name T243
Test name
Test status
Simulation time 4499480715 ps
CPU time 18.89 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 208960 kb
Host smart-415b8d17-3b02-4fb0-90bf-f4bdbd55601e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168060512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2168060512
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4113887728
Short name T419
Test name
Test status
Simulation time 296458853 ps
CPU time 1.9 seconds
Started Jul 29 05:02:15 PM PDT 24
Finished Jul 29 05:02:17 PM PDT 24
Peak memory 208384 kb
Host smart-67af2e26-11ff-495b-9f45-f71c5ee6e5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113887728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4113887728
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2594749220
Short name T306
Test name
Test status
Simulation time 118315500 ps
CPU time 1.11 seconds
Started Jul 29 05:02:17 PM PDT 24
Finished Jul 29 05:02:19 PM PDT 24
Peak memory 200204 kb
Host smart-dea7e7af-7c16-4322-8aba-74e7194a6930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594749220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2594749220
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.424225643
Short name T86
Test name
Test status
Simulation time 73165727 ps
CPU time 0.79 seconds
Started Jul 29 05:02:25 PM PDT 24
Finished Jul 29 05:02:26 PM PDT 24
Peak memory 200080 kb
Host smart-f584876f-05bd-424a-b77c-49743863e531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424225643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.424225643
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3709450367
Short name T36
Test name
Test status
Simulation time 2174380636 ps
CPU time 7.57 seconds
Started Jul 29 05:02:29 PM PDT 24
Finished Jul 29 05:02:37 PM PDT 24
Peak memory 217768 kb
Host smart-2c059ac3-0740-4d1c-ad53-f10ab771ea11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709450367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3709450367
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1178155293
Short name T398
Test name
Test status
Simulation time 244910355 ps
CPU time 1.16 seconds
Started Jul 29 05:02:19 PM PDT 24
Finished Jul 29 05:02:21 PM PDT 24
Peak memory 217436 kb
Host smart-6f137a87-b7e8-4a26-a997-47b429b7be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178155293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1178155293
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3047668964
Short name T539
Test name
Test status
Simulation time 210155835 ps
CPU time 0.98 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:15 PM PDT 24
Peak memory 200004 kb
Host smart-881dabba-8767-4e39-b2fb-959c09bb5c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047668964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3047668964
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.609193624
Short name T105
Test name
Test status
Simulation time 929671021 ps
CPU time 4.78 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:19 PM PDT 24
Peak memory 200508 kb
Host smart-4f7e2306-6049-454d-b757-6637d9b362c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609193624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.609193624
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3959575011
Short name T476
Test name
Test status
Simulation time 187869839 ps
CPU time 1.28 seconds
Started Jul 29 05:02:25 PM PDT 24
Finished Jul 29 05:02:26 PM PDT 24
Peak memory 200204 kb
Host smart-b45811f6-c81a-4d37-b1a2-1621f7d81676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959575011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3959575011
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3513336897
Short name T139
Test name
Test status
Simulation time 115623975 ps
CPU time 1.18 seconds
Started Jul 29 05:02:14 PM PDT 24
Finished Jul 29 05:02:15 PM PDT 24
Peak memory 200308 kb
Host smart-a3dd965d-3760-466b-b97b-4b423826f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513336897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3513336897
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2248281275
Short name T461
Test name
Test status
Simulation time 1442116728 ps
CPU time 6.42 seconds
Started Jul 29 05:02:23 PM PDT 24
Finished Jul 29 05:02:29 PM PDT 24
Peak memory 200444 kb
Host smart-2d68e562-0ad8-4921-9018-a3b2188a9c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248281275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2248281275
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3136936433
Short name T244
Test name
Test status
Simulation time 129159884 ps
CPU time 1.61 seconds
Started Jul 29 05:02:22 PM PDT 24
Finished Jul 29 05:02:23 PM PDT 24
Peak memory 200184 kb
Host smart-031936ca-3a94-4efc-8dd0-dfca5f1a5912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136936433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3136936433
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.975804038
Short name T323
Test name
Test status
Simulation time 64079588 ps
CPU time 0.77 seconds
Started Jul 29 05:02:20 PM PDT 24
Finished Jul 29 05:02:21 PM PDT 24
Peak memory 199992 kb
Host smart-db18a87a-0656-4b13-888e-6d62f426d35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975804038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.975804038
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.561820045
Short name T470
Test name
Test status
Simulation time 1226837951 ps
CPU time 5.57 seconds
Started Jul 29 05:02:22 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 217268 kb
Host smart-e8aabd0a-bad3-4c27-a887-8a361099a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561820045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.561820045
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1891482065
Short name T426
Test name
Test status
Simulation time 243948804 ps
CPU time 1.06 seconds
Started Jul 29 05:02:21 PM PDT 24
Finished Jul 29 05:02:22 PM PDT 24
Peak memory 217480 kb
Host smart-edccba7b-a2ce-48f7-955e-1b5202d36314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891482065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1891482065
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1782751024
Short name T290
Test name
Test status
Simulation time 82236890 ps
CPU time 0.73 seconds
Started Jul 29 05:02:21 PM PDT 24
Finished Jul 29 05:02:22 PM PDT 24
Peak memory 200140 kb
Host smart-b3a9c9d4-1a27-46a9-8ec1-3c47d9ef5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782751024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1782751024
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1342536308
Short name T284
Test name
Test status
Simulation time 1460668722 ps
CPU time 6.02 seconds
Started Jul 29 05:02:22 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 200448 kb
Host smart-948585b8-e626-4fc6-b6fd-abe5f10ff872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342536308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1342536308
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1004732872
Short name T256
Test name
Test status
Simulation time 180239202 ps
CPU time 1.26 seconds
Started Jul 29 05:02:21 PM PDT 24
Finished Jul 29 05:02:23 PM PDT 24
Peak memory 200216 kb
Host smart-45a168b1-f143-4cfb-afd5-71a834fe99ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004732872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1004732872
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.121603446
Short name T156
Test name
Test status
Simulation time 214076686 ps
CPU time 1.35 seconds
Started Jul 29 05:02:19 PM PDT 24
Finished Jul 29 05:02:21 PM PDT 24
Peak memory 200364 kb
Host smart-33eca1c6-01f8-43b0-b64c-601e08edbbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121603446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.121603446
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3364059237
Short name T250
Test name
Test status
Simulation time 7927300626 ps
CPU time 28.47 seconds
Started Jul 29 05:02:20 PM PDT 24
Finished Jul 29 05:02:48 PM PDT 24
Peak memory 200532 kb
Host smart-c8264498-408d-4849-a51b-a16720addc48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364059237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3364059237
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2668833727
Short name T392
Test name
Test status
Simulation time 540419954 ps
CPU time 2.71 seconds
Started Jul 29 05:02:26 PM PDT 24
Finished Jul 29 05:02:29 PM PDT 24
Peak memory 200220 kb
Host smart-b5407d1b-f883-4a3a-a478-526620e98eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668833727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2668833727
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1840716799
Short name T174
Test name
Test status
Simulation time 188118936 ps
CPU time 1.21 seconds
Started Jul 29 05:02:21 PM PDT 24
Finished Jul 29 05:02:22 PM PDT 24
Peak memory 200272 kb
Host smart-9a4897ed-c56e-4b43-ab38-83751657dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840716799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1840716799
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2318563216
Short name T453
Test name
Test status
Simulation time 76329419 ps
CPU time 0.8 seconds
Started Jul 29 05:02:25 PM PDT 24
Finished Jul 29 05:02:26 PM PDT 24
Peak memory 200072 kb
Host smart-36f9c270-8c8c-404f-bf3c-5754db1fcf5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318563216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2318563216
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.817569650
Short name T542
Test name
Test status
Simulation time 1886251178 ps
CPU time 7.87 seconds
Started Jul 29 05:02:26 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 217392 kb
Host smart-5f6121d7-0f65-4e55-a4ce-741e846a9252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817569650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.817569650
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4247315973
Short name T410
Test name
Test status
Simulation time 243488556 ps
CPU time 1.07 seconds
Started Jul 29 05:02:27 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 217396 kb
Host smart-02a29c5b-e2eb-4d05-8da8-9dccdcc50a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247315973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4247315973
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1529051302
Short name T384
Test name
Test status
Simulation time 141872116 ps
CPU time 0.83 seconds
Started Jul 29 05:02:27 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 200072 kb
Host smart-5c078ddd-c6de-47ca-a539-38e834985ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529051302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1529051302
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1003920841
Short name T433
Test name
Test status
Simulation time 1679536466 ps
CPU time 6.87 seconds
Started Jul 29 05:02:27 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 200412 kb
Host smart-cf66b20d-5130-41bd-a980-c3f50eb4d44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003920841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1003920841
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.308354988
Short name T267
Test name
Test status
Simulation time 101702644 ps
CPU time 0.99 seconds
Started Jul 29 05:02:26 PM PDT 24
Finished Jul 29 05:02:27 PM PDT 24
Peak memory 200292 kb
Host smart-6d46263f-de91-47fc-97c4-4b122c316e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308354988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.308354988
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3717567328
Short name T254
Test name
Test status
Simulation time 125272313 ps
CPU time 1.22 seconds
Started Jul 29 05:02:27 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 200364 kb
Host smart-c2661512-c01e-42b8-b729-433ad479ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717567328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3717567328
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1580637424
Short name T286
Test name
Test status
Simulation time 235615209 ps
CPU time 1.59 seconds
Started Jul 29 05:02:29 PM PDT 24
Finished Jul 29 05:02:31 PM PDT 24
Peak memory 200292 kb
Host smart-a8816b65-ed47-4ef9-89b2-db981a1f7d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580637424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1580637424
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.4275503662
Short name T366
Test name
Test status
Simulation time 131954081 ps
CPU time 1.64 seconds
Started Jul 29 05:02:28 PM PDT 24
Finished Jul 29 05:02:30 PM PDT 24
Peak memory 208412 kb
Host smart-ef385697-f3b4-4a48-a6cf-7c1e48b75ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275503662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4275503662
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3376353928
Short name T467
Test name
Test status
Simulation time 131115090 ps
CPU time 1.02 seconds
Started Jul 29 05:02:26 PM PDT 24
Finished Jul 29 05:02:27 PM PDT 24
Peak memory 200492 kb
Host smart-aa0d65b4-806d-4819-bde4-791bbf1d506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376353928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3376353928
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2545260813
Short name T175
Test name
Test status
Simulation time 84950582 ps
CPU time 0.86 seconds
Started Jul 29 05:02:32 PM PDT 24
Finished Jul 29 05:02:33 PM PDT 24
Peak memory 199972 kb
Host smart-f70c4828-7c82-499a-b280-86f8e5541e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545260813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2545260813
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4106814353
Short name T62
Test name
Test status
Simulation time 1885579274 ps
CPU time 7.92 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:41 PM PDT 24
Peak memory 217664 kb
Host smart-cfa4e823-92d7-4872-9193-e4a304c0c8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106814353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4106814353
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2564915316
Short name T532
Test name
Test status
Simulation time 244458539 ps
CPU time 1.09 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 217376 kb
Host smart-9acc6a4b-5100-46f4-a0f4-3803b08f50b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564915316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2564915316
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.199922735
Short name T19
Test name
Test status
Simulation time 186617672 ps
CPU time 0.89 seconds
Started Jul 29 05:02:27 PM PDT 24
Finished Jul 29 05:02:28 PM PDT 24
Peak memory 200020 kb
Host smart-9fd770f1-97f1-4689-b790-99d38c6e8691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199922735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.199922735
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2226438941
Short name T107
Test name
Test status
Simulation time 1038906423 ps
CPU time 5.1 seconds
Started Jul 29 05:02:29 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 200364 kb
Host smart-1ed88d49-be46-46e1-a9d2-2a8925817bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226438941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2226438941
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3032237870
Short name T349
Test name
Test status
Simulation time 104700072 ps
CPU time 1.01 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:35 PM PDT 24
Peak memory 200216 kb
Host smart-54e62d5c-f89e-4213-b550-3a9b52db4f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032237870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3032237870
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2000997243
Short name T387
Test name
Test status
Simulation time 190739563 ps
CPU time 1.49 seconds
Started Jul 29 05:02:25 PM PDT 24
Finished Jul 29 05:02:27 PM PDT 24
Peak memory 200384 kb
Host smart-cd0740f4-f4d5-437e-987c-a3efcdcb8ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000997243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2000997243
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1514486044
Short name T449
Test name
Test status
Simulation time 1905132216 ps
CPU time 7.75 seconds
Started Jul 29 05:02:32 PM PDT 24
Finished Jul 29 05:02:40 PM PDT 24
Peak memory 208564 kb
Host smart-fc8a7178-7c60-4807-b31e-011c6c056113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514486044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1514486044
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3750969817
Short name T266
Test name
Test status
Simulation time 130245893 ps
CPU time 1.75 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:35 PM PDT 24
Peak memory 200100 kb
Host smart-17c5598a-2049-48e5-810f-74e1f01dd3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750969817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3750969817
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3235189576
Short name T132
Test name
Test status
Simulation time 200524960 ps
CPU time 1.26 seconds
Started Jul 29 05:02:32 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 200156 kb
Host smart-ea27f785-cffa-4738-90bf-e748d027e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235189576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3235189576
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3781720954
Short name T540
Test name
Test status
Simulation time 61492406 ps
CPU time 0.78 seconds
Started Jul 29 05:02:36 PM PDT 24
Finished Jul 29 05:02:37 PM PDT 24
Peak memory 200084 kb
Host smart-19d934ef-b469-4e95-9988-1e4943491e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781720954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3781720954
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3236655083
Short name T488
Test name
Test status
Simulation time 1227633858 ps
CPU time 5.34 seconds
Started Jul 29 05:02:32 PM PDT 24
Finished Jul 29 05:02:38 PM PDT 24
Peak memory 217628 kb
Host smart-a56211ed-630f-4611-8ef2-a21f99e163b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236655083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3236655083
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2117480408
Short name T359
Test name
Test status
Simulation time 243614813 ps
CPU time 1.09 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 217428 kb
Host smart-b907ac02-bddc-4186-9af7-dce947c07ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117480408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2117480408
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3625997333
Short name T334
Test name
Test status
Simulation time 165915498 ps
CPU time 0.91 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 200108 kb
Host smart-fa7b4008-5c7e-4128-88ff-74f3fca07d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625997333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3625997333
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.981598262
Short name T357
Test name
Test status
Simulation time 867244252 ps
CPU time 4.44 seconds
Started Jul 29 05:02:33 PM PDT 24
Finished Jul 29 05:02:37 PM PDT 24
Peak memory 200300 kb
Host smart-5910ea87-285b-41ba-9d54-1ee6da4ca259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981598262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.981598262
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2456069391
Short name T326
Test name
Test status
Simulation time 155901325 ps
CPU time 1.18 seconds
Started Jul 29 05:02:32 PM PDT 24
Finished Jul 29 05:02:33 PM PDT 24
Peak memory 200228 kb
Host smart-17c872c5-de41-46ba-af76-603dac3ba2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456069391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2456069391
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1058446526
Short name T354
Test name
Test status
Simulation time 238824690 ps
CPU time 1.42 seconds
Started Jul 29 05:02:32 PM PDT 24
Finished Jul 29 05:02:33 PM PDT 24
Peak memory 200368 kb
Host smart-c7be4754-dae2-451a-9930-da5b4a546f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058446526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1058446526
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2881987146
Short name T309
Test name
Test status
Simulation time 17896257250 ps
CPU time 63.38 seconds
Started Jul 29 05:02:34 PM PDT 24
Finished Jul 29 05:03:38 PM PDT 24
Peak memory 200536 kb
Host smart-8bf4687f-36d3-4838-9c00-df31d9584368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881987146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2881987146
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2978662672
Short name T534
Test name
Test status
Simulation time 496693467 ps
CPU time 2.56 seconds
Started Jul 29 05:02:31 PM PDT 24
Finished Jul 29 05:02:34 PM PDT 24
Peak memory 200172 kb
Host smart-99647250-f3ab-48ed-a568-efafba497dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978662672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2978662672
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.307761123
Short name T180
Test name
Test status
Simulation time 179074095 ps
CPU time 1.23 seconds
Started Jul 29 05:02:34 PM PDT 24
Finished Jul 29 05:02:36 PM PDT 24
Peak memory 200328 kb
Host smart-83f333fe-f103-42f8-a98e-2b566d46f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307761123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.307761123
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3659079530
Short name T188
Test name
Test status
Simulation time 75408908 ps
CPU time 0.82 seconds
Started Jul 29 05:02:38 PM PDT 24
Finished Jul 29 05:02:39 PM PDT 24
Peak memory 200044 kb
Host smart-9e03b420-4690-414d-9ba4-2569829ab97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659079530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3659079530
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1540530985
Short name T314
Test name
Test status
Simulation time 1238947561 ps
CPU time 5.7 seconds
Started Jul 29 05:02:45 PM PDT 24
Finished Jul 29 05:02:51 PM PDT 24
Peak memory 221548 kb
Host smart-e4a6eb8b-ba81-4f3f-a7b9-6b33357a38cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540530985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1540530985
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2812904419
Short name T147
Test name
Test status
Simulation time 248523318 ps
CPU time 1.02 seconds
Started Jul 29 05:02:35 PM PDT 24
Finished Jul 29 05:02:37 PM PDT 24
Peak memory 217364 kb
Host smart-af50723d-32b9-49ea-9fce-05f08d8897ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812904419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2812904419
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3912027478
Short name T13
Test name
Test status
Simulation time 143816358 ps
CPU time 0.81 seconds
Started Jul 29 05:02:37 PM PDT 24
Finished Jul 29 05:02:38 PM PDT 24
Peak memory 199964 kb
Host smart-5640d4ff-843f-48d0-8ead-4180982cd203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912027478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3912027478
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1353737265
Short name T230
Test name
Test status
Simulation time 1983469470 ps
CPU time 7.07 seconds
Started Jul 29 05:02:39 PM PDT 24
Finished Jul 29 05:02:47 PM PDT 24
Peak memory 200376 kb
Host smart-52a80e76-248a-42e5-b6f2-b9c71e4ecaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353737265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1353737265
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4264660132
Short name T429
Test name
Test status
Simulation time 172820966 ps
CPU time 1.17 seconds
Started Jul 29 05:02:37 PM PDT 24
Finished Jul 29 05:02:38 PM PDT 24
Peak memory 200288 kb
Host smart-d959a345-b3c1-4a5a-99d3-743503534915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264660132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4264660132
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.105770
Short name T185
Test name
Test status
Simulation time 197203770 ps
CPU time 1.38 seconds
Started Jul 29 05:02:35 PM PDT 24
Finished Jul 29 05:02:37 PM PDT 24
Peak memory 200404 kb
Host smart-20fc3f3e-5a24-4a68-b3ea-bb93b85b7127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.105770
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.863614904
Short name T489
Test name
Test status
Simulation time 1924999563 ps
CPU time 6.86 seconds
Started Jul 29 05:02:40 PM PDT 24
Finished Jul 29 05:02:46 PM PDT 24
Peak memory 208744 kb
Host smart-a9c3c7ae-6376-4468-9f3c-563fe98f0724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863614904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.863614904
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.795405345
Short name T248
Test name
Test status
Simulation time 148693451 ps
CPU time 1.85 seconds
Started Jul 29 05:02:38 PM PDT 24
Finished Jul 29 05:02:39 PM PDT 24
Peak memory 200220 kb
Host smart-0e524fef-9b9f-4bd6-8136-5bd2d21a90de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795405345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.795405345
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2051102242
Short name T277
Test name
Test status
Simulation time 74151580 ps
CPU time 0.86 seconds
Started Jul 29 05:02:47 PM PDT 24
Finished Jul 29 05:02:48 PM PDT 24
Peak memory 200276 kb
Host smart-a1bcf0ea-68ec-4219-8047-885e75d79588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051102242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2051102242
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.663573997
Short name T356
Test name
Test status
Simulation time 81536173 ps
CPU time 0.81 seconds
Started Jul 29 05:02:43 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 200036 kb
Host smart-c4d2c3ee-47a8-4bc7-be7e-11874d7a316c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663573997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.663573997
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.893807087
Short name T305
Test name
Test status
Simulation time 1232453405 ps
CPU time 5.52 seconds
Started Jul 29 05:02:46 PM PDT 24
Finished Jul 29 05:02:52 PM PDT 24
Peak memory 217220 kb
Host smart-ee174927-5202-4e75-a8f5-6dd820e937b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893807087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.893807087
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1684453332
Short name T521
Test name
Test status
Simulation time 243541808 ps
CPU time 1.14 seconds
Started Jul 29 05:02:42 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 217380 kb
Host smart-c3e8ff1a-7efe-42dd-b370-02f134a98a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684453332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1684453332
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2660788056
Short name T21
Test name
Test status
Simulation time 102859356 ps
CPU time 0.78 seconds
Started Jul 29 05:02:43 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 199944 kb
Host smart-36b24bd3-a3b7-4a15-8636-d9335eac4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660788056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2660788056
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.327627871
Short name T2
Test name
Test status
Simulation time 1697884136 ps
CPU time 6.58 seconds
Started Jul 29 05:02:43 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 200312 kb
Host smart-4706cd63-8d13-4739-8e0a-9f726b9518c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327627871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.327627871
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3215529688
Short name T316
Test name
Test status
Simulation time 102191432 ps
CPU time 0.99 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 200276 kb
Host smart-39e99ac1-2233-4763-b348-2ecd2e868e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215529688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3215529688
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3584672709
Short name T347
Test name
Test status
Simulation time 245612176 ps
CPU time 1.54 seconds
Started Jul 29 05:02:38 PM PDT 24
Finished Jul 29 05:02:39 PM PDT 24
Peak memory 200452 kb
Host smart-53eee1ab-4ada-43af-a2b7-9ec2fced0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584672709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3584672709
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1703858877
Short name T103
Test name
Test status
Simulation time 3637719659 ps
CPU time 17.22 seconds
Started Jul 29 05:02:44 PM PDT 24
Finished Jul 29 05:03:01 PM PDT 24
Peak memory 200388 kb
Host smart-ef02e9da-186c-4c3a-baa1-9e457a729d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703858877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1703858877
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3778758352
Short name T340
Test name
Test status
Simulation time 129535487 ps
CPU time 1.77 seconds
Started Jul 29 05:02:43 PM PDT 24
Finished Jul 29 05:02:45 PM PDT 24
Peak memory 200140 kb
Host smart-b1d4d40e-5930-4cb7-bd9e-2c202e47556b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778758352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3778758352
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3867648082
Short name T172
Test name
Test status
Simulation time 244037555 ps
CPU time 1.48 seconds
Started Jul 29 05:02:44 PM PDT 24
Finished Jul 29 05:02:46 PM PDT 24
Peak memory 200408 kb
Host smart-3f5bcca6-5775-404c-b7cf-29cc41d429b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867648082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3867648082
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3322125889
Short name T319
Test name
Test status
Simulation time 74318649 ps
CPU time 0.8 seconds
Started Jul 29 05:02:45 PM PDT 24
Finished Jul 29 05:02:46 PM PDT 24
Peak memory 200084 kb
Host smart-4900d4c7-6dab-4af2-959f-ca912601c686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322125889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3322125889
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.106191104
Short name T414
Test name
Test status
Simulation time 1906541648 ps
CPU time 7.34 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:03:01 PM PDT 24
Peak memory 217468 kb
Host smart-ecc99ae1-05f6-4883-ae8e-d4a702232cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106191104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.106191104
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.671230152
Short name T440
Test name
Test status
Simulation time 245524264 ps
CPU time 1.16 seconds
Started Jul 29 05:02:44 PM PDT 24
Finished Jul 29 05:02:45 PM PDT 24
Peak memory 217432 kb
Host smart-bf0bbc6b-1346-4011-8972-5bc04d5f56ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671230152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.671230152
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.644957938
Short name T17
Test name
Test status
Simulation time 101869243 ps
CPU time 0.79 seconds
Started Jul 29 05:02:43 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 200288 kb
Host smart-34669311-cc78-4561-96b4-d82bfd5a2a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644957938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.644957938
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3912391833
Short name T108
Test name
Test status
Simulation time 1456042574 ps
CPU time 6.12 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:02:59 PM PDT 24
Peak memory 200484 kb
Host smart-b0467e8b-19d4-4a8c-b1cc-a1c809afa8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912391833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3912391833
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.505112607
Short name T408
Test name
Test status
Simulation time 97447843 ps
CPU time 1 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 200276 kb
Host smart-bedb6573-855e-4ba4-90fc-3c20e16149c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505112607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.505112607
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.912437083
Short name T191
Test name
Test status
Simulation time 117773846 ps
CPU time 1.24 seconds
Started Jul 29 05:02:43 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 200320 kb
Host smart-b8539738-1864-47d8-817c-50f657bcc15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912437083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.912437083
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3994834189
Short name T130
Test name
Test status
Simulation time 8827342337 ps
CPU time 29.7 seconds
Started Jul 29 05:02:42 PM PDT 24
Finished Jul 29 05:03:12 PM PDT 24
Peak memory 208596 kb
Host smart-36568357-7b9e-46d7-aebb-99b8f825739c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994834189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3994834189
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4208244078
Short name T464
Test name
Test status
Simulation time 457238013 ps
CPU time 2.43 seconds
Started Jul 29 05:02:47 PM PDT 24
Finished Jul 29 05:02:49 PM PDT 24
Peak memory 200116 kb
Host smart-cfcca3c0-a90d-4df4-989a-ddfae995b90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208244078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4208244078
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3974058981
Short name T210
Test name
Test status
Simulation time 143158364 ps
CPU time 1.14 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:02:54 PM PDT 24
Peak memory 200276 kb
Host smart-361a118a-6464-434e-87e1-14a1457db9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974058981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3974058981
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.52060395
Short name T143
Test name
Test status
Simulation time 60864513 ps
CPU time 0.79 seconds
Started Jul 29 05:02:51 PM PDT 24
Finished Jul 29 05:02:52 PM PDT 24
Peak memory 200024 kb
Host smart-07ca0e0a-2219-48e4-a9dd-d51596d056dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52060395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.52060395
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2558199584
Short name T30
Test name
Test status
Simulation time 1219867977 ps
CPU time 5.65 seconds
Started Jul 29 05:02:58 PM PDT 24
Finished Jul 29 05:03:04 PM PDT 24
Peak memory 217352 kb
Host smart-879a788a-713d-4a06-9c98-ca1a86e5d175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558199584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2558199584
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2624789055
Short name T299
Test name
Test status
Simulation time 244315346 ps
CPU time 1.17 seconds
Started Jul 29 05:02:47 PM PDT 24
Finished Jul 29 05:02:48 PM PDT 24
Peak memory 217508 kb
Host smart-19d594ec-5345-4d29-a84a-21fafa73c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624789055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2624789055
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.688608626
Short name T344
Test name
Test status
Simulation time 84121410 ps
CPU time 0.76 seconds
Started Jul 29 05:02:44 PM PDT 24
Finished Jul 29 05:02:45 PM PDT 24
Peak memory 200092 kb
Host smart-0cbace00-318a-4f41-8316-b38b7dd4d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688608626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.688608626
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2126363873
Short name T497
Test name
Test status
Simulation time 1633622842 ps
CPU time 6.71 seconds
Started Jul 29 05:02:44 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 200300 kb
Host smart-44c4e28e-6757-4c28-aeb1-507ba9b26c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126363873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2126363873
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.261886406
Short name T206
Test name
Test status
Simulation time 142276351 ps
CPU time 1.14 seconds
Started Jul 29 05:02:42 PM PDT 24
Finished Jul 29 05:02:44 PM PDT 24
Peak memory 200220 kb
Host smart-7381f89b-49f2-409a-b3e8-6e50e50776a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261886406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.261886406
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1287261885
Short name T511
Test name
Test status
Simulation time 116748514 ps
CPU time 1.15 seconds
Started Jul 29 05:02:45 PM PDT 24
Finished Jul 29 05:02:46 PM PDT 24
Peak memory 200296 kb
Host smart-534d382f-fb52-4d5c-8ff9-4c624a26ee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287261885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1287261885
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.334029423
Short name T459
Test name
Test status
Simulation time 141080936 ps
CPU time 1.09 seconds
Started Jul 29 05:02:51 PM PDT 24
Finished Jul 29 05:02:52 PM PDT 24
Peak memory 200208 kb
Host smart-994169c5-8d51-4bab-92b4-3c6e01a122a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334029423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.334029423
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3187614646
Short name T241
Test name
Test status
Simulation time 149416295 ps
CPU time 1.05 seconds
Started Jul 29 05:02:42 PM PDT 24
Finished Jul 29 05:02:43 PM PDT 24
Peak memory 200200 kb
Host smart-f50b714d-b2c6-474e-a2c7-52e1f898dcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187614646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3187614646
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.109340959
Short name T285
Test name
Test status
Simulation time 326153763 ps
CPU time 1.36 seconds
Started Jul 29 05:00:34 PM PDT 24
Finished Jul 29 05:00:35 PM PDT 24
Peak memory 200144 kb
Host smart-54860c68-dd82-432f-bf07-ec429287e39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109340959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.109340959
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3723542023
Short name T362
Test name
Test status
Simulation time 1900369684 ps
CPU time 6.85 seconds
Started Jul 29 05:00:33 PM PDT 24
Finished Jul 29 05:00:40 PM PDT 24
Peak memory 217528 kb
Host smart-89dfddcc-202e-47e0-8df4-4a3afd8729fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723542023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3723542023
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1039305832
Short name T265
Test name
Test status
Simulation time 244289301 ps
CPU time 1.07 seconds
Started Jul 29 05:00:36 PM PDT 24
Finished Jul 29 05:00:37 PM PDT 24
Peak memory 217336 kb
Host smart-2ebed878-6d62-463e-9613-d968ec04eea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039305832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1039305832
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3554576546
Short name T352
Test name
Test status
Simulation time 121734270 ps
CPU time 0.81 seconds
Started Jul 29 05:00:22 PM PDT 24
Finished Jul 29 05:00:23 PM PDT 24
Peak memory 200088 kb
Host smart-d9e850a3-d4d2-46e9-a0d3-0d9ba2e95fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554576546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3554576546
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2581658389
Short name T425
Test name
Test status
Simulation time 1046878088 ps
CPU time 5.26 seconds
Started Jul 29 05:00:32 PM PDT 24
Finished Jul 29 05:00:37 PM PDT 24
Peak memory 200324 kb
Host smart-13c21f7a-8739-48cf-927a-d8c2a7ae4caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581658389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2581658389
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1758516619
Short name T77
Test name
Test status
Simulation time 16518290051 ps
CPU time 28.16 seconds
Started Jul 29 05:00:32 PM PDT 24
Finished Jul 29 05:01:00 PM PDT 24
Peak memory 217120 kb
Host smart-f1572fc4-2205-40f3-b344-e4609328d4e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758516619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1758516619
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2448991753
Short name T291
Test name
Test status
Simulation time 94814123 ps
CPU time 1.05 seconds
Started Jul 29 05:00:27 PM PDT 24
Finished Jul 29 05:00:28 PM PDT 24
Peak memory 200152 kb
Host smart-3aa710d5-e05e-4425-9b29-e54b8729f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448991753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2448991753
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.761740531
Short name T428
Test name
Test status
Simulation time 242700964 ps
CPU time 1.55 seconds
Started Jul 29 05:00:22 PM PDT 24
Finished Jul 29 05:00:24 PM PDT 24
Peak memory 200240 kb
Host smart-c1dfdc4f-9092-453b-8848-ffd01dbbcda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761740531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.761740531
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1472252758
Short name T320
Test name
Test status
Simulation time 1583464416 ps
CPU time 7.04 seconds
Started Jul 29 05:00:35 PM PDT 24
Finished Jul 29 05:00:42 PM PDT 24
Peak memory 200528 kb
Host smart-6a5e7095-1d67-44ad-89ad-dabca97eafdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472252758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1472252758
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1747851638
Short name T39
Test name
Test status
Simulation time 487191728 ps
CPU time 2.7 seconds
Started Jul 29 05:00:31 PM PDT 24
Finished Jul 29 05:00:34 PM PDT 24
Peak memory 200252 kb
Host smart-4dedb183-6e32-4dc8-b5ab-af5b6687a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747851638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1747851638
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4074764941
Short name T151
Test name
Test status
Simulation time 277651343 ps
CPU time 1.64 seconds
Started Jul 29 05:00:27 PM PDT 24
Finished Jul 29 05:00:28 PM PDT 24
Peak memory 200240 kb
Host smart-bcb560a8-4d9a-4d6d-add1-d692d08146de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074764941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4074764941
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3667425903
Short name T303
Test name
Test status
Simulation time 81581172 ps
CPU time 0.88 seconds
Started Jul 29 05:02:48 PM PDT 24
Finished Jul 29 05:02:49 PM PDT 24
Peak memory 200016 kb
Host smart-e605922e-3715-4ca9-a6df-daa3cd5041af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667425903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3667425903
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1205220384
Short name T46
Test name
Test status
Simulation time 2367418618 ps
CPU time 8.38 seconds
Started Jul 29 05:02:47 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 221668 kb
Host smart-772b7156-424d-4ad3-af5a-bce885a54211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205220384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1205220384
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2982145048
Short name T415
Test name
Test status
Simulation time 243783961 ps
CPU time 1.13 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 217432 kb
Host smart-06e48e1f-ab96-4f18-85ee-95c0d0db6134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982145048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2982145048
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4079858465
Short name T514
Test name
Test status
Simulation time 77647726 ps
CPU time 0.75 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 199948 kb
Host smart-d5a9008c-432d-41db-96f8-62d760b069ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079858465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4079858465
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.142877911
Short name T102
Test name
Test status
Simulation time 1834082479 ps
CPU time 6.68 seconds
Started Jul 29 05:02:56 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 200392 kb
Host smart-65ce3bf0-33a5-4a2f-8b9a-f7ce8afd6306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142877911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.142877911
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1764205295
Short name T371
Test name
Test status
Simulation time 160992910 ps
CPU time 1.15 seconds
Started Jul 29 05:02:48 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 200280 kb
Host smart-dd70b758-999d-40cf-b642-e322b3c5c0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764205295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1764205295
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3507405138
Short name T219
Test name
Test status
Simulation time 189696963 ps
CPU time 1.48 seconds
Started Jul 29 05:02:48 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 200372 kb
Host smart-aa013d88-3368-4a9e-8616-c65258de4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507405138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3507405138
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3521072345
Short name T12
Test name
Test status
Simulation time 7569463219 ps
CPU time 34.32 seconds
Started Jul 29 05:02:50 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 208724 kb
Host smart-86a164a1-3746-4fa6-8fe5-a6592bc4a50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521072345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3521072345
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1938330905
Short name T91
Test name
Test status
Simulation time 362913419 ps
CPU time 2.33 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:51 PM PDT 24
Peak memory 200132 kb
Host smart-fa84e31a-a5e7-436c-b9a4-7223c9a8a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938330905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1938330905
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.901112508
Short name T192
Test name
Test status
Simulation time 205284408 ps
CPU time 1.42 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:51 PM PDT 24
Peak memory 200284 kb
Host smart-0c9233ab-518a-4fae-8254-8c4acf41ce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901112508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.901112508
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3251342717
Short name T337
Test name
Test status
Simulation time 71621320 ps
CPU time 0.8 seconds
Started Jul 29 05:02:48 PM PDT 24
Finished Jul 29 05:02:49 PM PDT 24
Peak memory 200084 kb
Host smart-4f342ac6-1038-4575-8964-842592641efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251342717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3251342717
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3862064899
Short name T67
Test name
Test status
Simulation time 1229213049 ps
CPU time 5.61 seconds
Started Jul 29 05:02:51 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 221612 kb
Host smart-63040dcc-0060-4ea6-bf64-91a4909bb8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862064899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3862064899
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2537777772
Short name T480
Test name
Test status
Simulation time 243948707 ps
CPU time 1.09 seconds
Started Jul 29 05:02:56 PM PDT 24
Finished Jul 29 05:02:57 PM PDT 24
Peak memory 217316 kb
Host smart-b4882c22-c513-46f3-8a84-0fef1ed461d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537777772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2537777772
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1653609162
Short name T368
Test name
Test status
Simulation time 83575314 ps
CPU time 0.76 seconds
Started Jul 29 05:02:51 PM PDT 24
Finished Jul 29 05:02:51 PM PDT 24
Peak memory 200040 kb
Host smart-2ed7a600-fa5e-49a4-8f3c-20ef3b776ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653609162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1653609162
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.861262342
Short name T504
Test name
Test status
Simulation time 1177368605 ps
CPU time 5.52 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 200480 kb
Host smart-757d5e1e-d6b2-478c-8fdc-941d5a3b0ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861262342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.861262342
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4137890875
Short name T300
Test name
Test status
Simulation time 155191463 ps
CPU time 1.19 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:50 PM PDT 24
Peak memory 200280 kb
Host smart-f54b434b-82f3-417d-8644-e582dd816042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137890875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4137890875
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2124538028
Short name T346
Test name
Test status
Simulation time 114692068 ps
CPU time 1.26 seconds
Started Jul 29 05:02:52 PM PDT 24
Finished Jul 29 05:02:53 PM PDT 24
Peak memory 200276 kb
Host smart-d29082ae-abf0-4dc3-9c90-e7d8e72a896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124538028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2124538028
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1539054525
Short name T287
Test name
Test status
Simulation time 15580149403 ps
CPU time 56.85 seconds
Started Jul 29 05:02:48 PM PDT 24
Finished Jul 29 05:03:45 PM PDT 24
Peak memory 200364 kb
Host smart-828dca66-afb0-47d8-a37e-f644dc413ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539054525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1539054525
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2681285935
Short name T187
Test name
Test status
Simulation time 386913090 ps
CPU time 2.42 seconds
Started Jul 29 05:02:49 PM PDT 24
Finished Jul 29 05:02:51 PM PDT 24
Peak memory 200232 kb
Host smart-5e35e177-67c8-4fe6-9077-9d7d6b264454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681285935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2681285935
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3685040498
Short name T186
Test name
Test status
Simulation time 191405220 ps
CPU time 1.27 seconds
Started Jul 29 05:02:51 PM PDT 24
Finished Jul 29 05:02:52 PM PDT 24
Peak memory 200216 kb
Host smart-e20d0b53-303a-4dff-8d76-1235e1252125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685040498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3685040498
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3284894143
Short name T393
Test name
Test status
Simulation time 71859104 ps
CPU time 0.81 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200072 kb
Host smart-b9424bc2-ae87-469d-a72c-1f13aa7d0422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284894143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3284894143
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4078275898
Short name T501
Test name
Test status
Simulation time 1234371123 ps
CPU time 5.85 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:02:59 PM PDT 24
Peak memory 220656 kb
Host smart-519a7960-cb98-4e75-b487-477bf4964229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078275898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4078275898
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.678224082
Short name T522
Test name
Test status
Simulation time 247485650 ps
CPU time 1.08 seconds
Started Jul 29 05:02:51 PM PDT 24
Finished Jul 29 05:02:53 PM PDT 24
Peak memory 217460 kb
Host smart-48f6cdb4-4a11-419c-94d6-c218ab9be1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678224082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.678224082
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3137711561
Short name T264
Test name
Test status
Simulation time 94072578 ps
CPU time 0.75 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 199972 kb
Host smart-de9eb3f8-9e45-48be-b36d-bbdd5c359c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137711561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3137711561
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2365688011
Short name T204
Test name
Test status
Simulation time 1024911886 ps
CPU time 5.23 seconds
Started Jul 29 05:03:00 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 200384 kb
Host smart-2579edd1-6192-4f41-8f51-1343f92b5907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365688011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2365688011
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.540116306
Short name T207
Test name
Test status
Simulation time 148523269 ps
CPU time 1.15 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:02:54 PM PDT 24
Peak memory 200200 kb
Host smart-72f4bd4c-2889-42bd-a3ae-966020343cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540116306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.540116306
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2740418388
Short name T41
Test name
Test status
Simulation time 251533713 ps
CPU time 1.57 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200424 kb
Host smart-3e07a7d3-a6cb-4736-a5c3-6e349283d8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740418388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2740418388
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2657529782
Short name T231
Test name
Test status
Simulation time 841445805 ps
CPU time 3.43 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200452 kb
Host smart-d11f42a3-ae6d-489a-b609-47848cf028e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657529782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2657529782
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1046092567
Short name T22
Test name
Test status
Simulation time 138608321 ps
CPU time 1.64 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:02:57 PM PDT 24
Peak memory 200252 kb
Host smart-dcc5eb05-4163-4e7d-a9d6-9df9af02a7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046092567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1046092567
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3224367501
Short name T412
Test name
Test status
Simulation time 152787579 ps
CPU time 1.37 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200268 kb
Host smart-7bff2aac-6e37-4f95-899b-8f6dffaf35dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224367501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3224367501
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2723396194
Short name T441
Test name
Test status
Simulation time 67073743 ps
CPU time 0.78 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200044 kb
Host smart-20456a09-ae5c-412b-98ef-6ef0bb39bdb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723396194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2723396194
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3895135949
Short name T1
Test name
Test status
Simulation time 1213129433 ps
CPU time 5.98 seconds
Started Jul 29 05:03:00 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 217668 kb
Host smart-4c4fe07f-5769-4400-9a3e-3f57be71a049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895135949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3895135949
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.12169309
Short name T236
Test name
Test status
Simulation time 245197897 ps
CPU time 1.05 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 217432 kb
Host smart-37b08ebe-656c-45e1-a1fb-093e376e1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12169309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.12169309
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2110357941
Short name T500
Test name
Test status
Simulation time 193082578 ps
CPU time 0.88 seconds
Started Jul 29 05:03:00 PM PDT 24
Finished Jul 29 05:03:01 PM PDT 24
Peak memory 200072 kb
Host smart-a70a3b3c-5916-4b02-8184-e2ffba34f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110357941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2110357941
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.530990331
Short name T198
Test name
Test status
Simulation time 1104197017 ps
CPU time 4.98 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:59 PM PDT 24
Peak memory 200424 kb
Host smart-066741be-a879-4e39-9787-01870658fe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530990331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.530990331
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3975188656
Short name T223
Test name
Test status
Simulation time 168149369 ps
CPU time 1.14 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200196 kb
Host smart-707cb390-0e80-402e-b9dc-da0aba2ee5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975188656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3975188656
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2441547544
Short name T154
Test name
Test status
Simulation time 124949417 ps
CPU time 1.15 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 200376 kb
Host smart-5ed27e3a-7b3d-4589-b94b-08dd61af1f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441547544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2441547544
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1895579685
Short name T161
Test name
Test status
Simulation time 7582005091 ps
CPU time 27.1 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:03:22 PM PDT 24
Peak memory 208736 kb
Host smart-ad7bdcc2-b8a4-4e4e-8a8b-7b8239e06a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895579685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1895579685
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2202519678
Short name T193
Test name
Test status
Simulation time 457363468 ps
CPU time 2.52 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200080 kb
Host smart-b3be0937-def6-4dd0-917d-9e8d4e0766c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202519678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2202519678
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4254818548
Short name T421
Test name
Test status
Simulation time 261408833 ps
CPU time 1.55 seconds
Started Jul 29 05:03:01 PM PDT 24
Finished Jul 29 05:03:02 PM PDT 24
Peak memory 200268 kb
Host smart-c951011c-3bae-442e-8353-2854d0b2cdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254818548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4254818548
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.506047739
Short name T487
Test name
Test status
Simulation time 59647921 ps
CPU time 0.75 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 200088 kb
Host smart-33dda21c-3193-4a7e-ad3e-0acb9e00895b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506047739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.506047739
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1116465466
Short name T31
Test name
Test status
Simulation time 1898458415 ps
CPU time 7.83 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:03:02 PM PDT 24
Peak memory 217604 kb
Host smart-d33b0e5b-c188-4c03-80da-b69a1efa6a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116465466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1116465466
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2437668852
Short name T367
Test name
Test status
Simulation time 244192382 ps
CPU time 1.05 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 217316 kb
Host smart-ba4d32f8-7f53-4d90-a5cd-6a6c05a10608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437668852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2437668852
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1408941130
Short name T195
Test name
Test status
Simulation time 77951683 ps
CPU time 0.74 seconds
Started Jul 29 05:03:01 PM PDT 24
Finished Jul 29 05:03:02 PM PDT 24
Peak memory 200072 kb
Host smart-9f5c69bb-d107-4273-a0d9-6bf46c8ed8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408941130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1408941130
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.786049675
Short name T509
Test name
Test status
Simulation time 1370081998 ps
CPU time 5.5 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:03:01 PM PDT 24
Peak memory 200380 kb
Host smart-7c6d51f0-1a89-44fd-92e6-c03615aa4f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786049675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.786049675
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3860904478
Short name T409
Test name
Test status
Simulation time 153027344 ps
CPU time 1.15 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200196 kb
Host smart-27dc5d2e-5beb-4f05-a2d7-8015c31a2b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860904478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3860904478
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.19071931
Short name T381
Test name
Test status
Simulation time 120618099 ps
CPU time 1.2 seconds
Started Jul 29 05:02:56 PM PDT 24
Finished Jul 29 05:02:57 PM PDT 24
Peak memory 200356 kb
Host smart-4dc5e51f-5302-4ff4-960f-e3ccd788e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19071931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.19071931
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2685629017
Short name T268
Test name
Test status
Simulation time 5841075039 ps
CPU time 20.25 seconds
Started Jul 29 05:02:53 PM PDT 24
Finished Jul 29 05:03:13 PM PDT 24
Peak memory 208596 kb
Host smart-71fd925e-774c-49df-85eb-71a40fbab6e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685629017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2685629017
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3668008652
Short name T307
Test name
Test status
Simulation time 485279689 ps
CPU time 2.42 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:02:57 PM PDT 24
Peak memory 200080 kb
Host smart-8dfcae89-a4a9-41fd-ac02-a83a5ff0361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668008652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3668008652
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.710947993
Short name T6
Test name
Test status
Simulation time 65200388 ps
CPU time 0.75 seconds
Started Jul 29 05:02:54 PM PDT 24
Finished Jul 29 05:02:55 PM PDT 24
Peak memory 200168 kb
Host smart-eaaede0e-189e-44f7-8026-62c82e28b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710947993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.710947993
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.509436457
Short name T205
Test name
Test status
Simulation time 71073536 ps
CPU time 0.76 seconds
Started Jul 29 05:03:00 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200028 kb
Host smart-9ede9b22-a978-441d-8837-969a55428876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509436457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.509436457
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2388835913
Short name T34
Test name
Test status
Simulation time 1226496532 ps
CPU time 5.92 seconds
Started Jul 29 05:02:57 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 221608 kb
Host smart-a7bef79e-9347-4054-9672-77d1ee09c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388835913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2388835913
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1362688173
Short name T310
Test name
Test status
Simulation time 243449297 ps
CPU time 1.07 seconds
Started Jul 29 05:03:02 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 217448 kb
Host smart-4cd0e15a-dc68-4f43-904b-5ccd3346ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362688173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1362688173
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1277862637
Short name T527
Test name
Test status
Simulation time 141655594 ps
CPU time 0.91 seconds
Started Jul 29 05:03:01 PM PDT 24
Finished Jul 29 05:03:02 PM PDT 24
Peak memory 200056 kb
Host smart-361101ff-5f98-48d6-b588-e9ed47a01767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277862637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1277862637
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2306173598
Short name T275
Test name
Test status
Simulation time 1459532676 ps
CPU time 6.82 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:05 PM PDT 24
Peak memory 200484 kb
Host smart-fc2a5cd4-54b7-4c0a-8c18-ebdda06d1b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306173598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2306173598
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.413525850
Short name T262
Test name
Test status
Simulation time 158655766 ps
CPU time 1.17 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200160 kb
Host smart-2afbb70d-1e8a-4e7e-ac05-d7e14170c489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413525850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.413525850
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3260928751
Short name T4
Test name
Test status
Simulation time 231083864 ps
CPU time 1.58 seconds
Started Jul 29 05:02:55 PM PDT 24
Finished Jul 29 05:02:56 PM PDT 24
Peak memory 200300 kb
Host smart-e2dd45ba-4a3a-4913-8bfe-5aa00a544243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260928751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3260928751
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.734770390
Short name T399
Test name
Test status
Simulation time 6058824736 ps
CPU time 28.66 seconds
Started Jul 29 05:03:01 PM PDT 24
Finished Jul 29 05:03:30 PM PDT 24
Peak memory 200528 kb
Host smart-7d7a121c-5218-48aa-b3cb-651dfa563419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734770390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.734770390
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3643897263
Short name T517
Test name
Test status
Simulation time 400874657 ps
CPU time 2.92 seconds
Started Jul 29 05:02:57 PM PDT 24
Finished Jul 29 05:03:01 PM PDT 24
Peak memory 200204 kb
Host smart-ef9704af-e855-469c-84b8-92df5500dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643897263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3643897263
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3306724494
Short name T401
Test name
Test status
Simulation time 151942081 ps
CPU time 1.29 seconds
Started Jul 29 05:02:57 PM PDT 24
Finished Jul 29 05:02:59 PM PDT 24
Peak memory 200240 kb
Host smart-194bcce3-e48f-4ab5-85bf-1d17ef69cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306724494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3306724494
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2124915239
Short name T529
Test name
Test status
Simulation time 79032301 ps
CPU time 0.83 seconds
Started Jul 29 05:03:03 PM PDT 24
Finished Jul 29 05:03:04 PM PDT 24
Peak memory 200100 kb
Host smart-b9844ed3-8572-4121-851c-48b2b84c36bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124915239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2124915239
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3254807348
Short name T526
Test name
Test status
Simulation time 1234630324 ps
CPU time 5.78 seconds
Started Jul 29 05:03:00 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 217532 kb
Host smart-0bfbd6e9-bef6-49dc-ae44-afb1beb91b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254807348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3254807348
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1140187202
Short name T150
Test name
Test status
Simulation time 246398686 ps
CPU time 1.05 seconds
Started Jul 29 05:03:10 PM PDT 24
Finished Jul 29 05:03:11 PM PDT 24
Peak memory 217412 kb
Host smart-ab4c7b43-9ec1-4961-a5ca-6f939819c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140187202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1140187202
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1091841313
Short name T317
Test name
Test status
Simulation time 201869618 ps
CPU time 0.96 seconds
Started Jul 29 05:02:58 PM PDT 24
Finished Jul 29 05:02:59 PM PDT 24
Peak memory 200072 kb
Host smart-46b53cb0-d05e-4952-96f0-280077d2c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091841313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1091841313
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1392885562
Short name T278
Test name
Test status
Simulation time 1394172628 ps
CPU time 5.56 seconds
Started Jul 29 05:03:00 PM PDT 24
Finished Jul 29 05:03:05 PM PDT 24
Peak memory 200408 kb
Host smart-c27c7319-d5ac-4e7a-85eb-e6d32ccef178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392885562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1392885562
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2058475161
Short name T218
Test name
Test status
Simulation time 158566562 ps
CPU time 1.16 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200340 kb
Host smart-d0e4f58a-65e4-435a-8ff7-15db9e45a51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058475161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2058475161
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1778881484
Short name T145
Test name
Test status
Simulation time 113870298 ps
CPU time 1.2 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200372 kb
Host smart-6b874492-f1e0-4eea-b23d-ba2fda372b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778881484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1778881484
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2029855356
Short name T228
Test name
Test status
Simulation time 1913702797 ps
CPU time 9.45 seconds
Started Jul 29 05:03:07 PM PDT 24
Finished Jul 29 05:03:16 PM PDT 24
Peak memory 208648 kb
Host smart-8dfd3061-79f9-49ed-871b-183df24d2870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029855356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2029855356
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1176768697
Short name T436
Test name
Test status
Simulation time 290332070 ps
CPU time 2.15 seconds
Started Jul 29 05:03:01 PM PDT 24
Finished Jul 29 05:03:03 PM PDT 24
Peak memory 200208 kb
Host smart-489b58a8-c887-418c-9699-b037ebbf938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176768697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1176768697
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2618262571
Short name T333
Test name
Test status
Simulation time 204314185 ps
CPU time 1.28 seconds
Started Jul 29 05:02:59 PM PDT 24
Finished Jul 29 05:03:00 PM PDT 24
Peak memory 200276 kb
Host smart-e4b245aa-df2f-40bf-8bcc-6ce9cfa93564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618262571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2618262571
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1300137741
Short name T312
Test name
Test status
Simulation time 60698176 ps
CPU time 0.76 seconds
Started Jul 29 05:03:11 PM PDT 24
Finished Jul 29 05:03:12 PM PDT 24
Peak memory 200084 kb
Host smart-d170cffa-f078-4be9-9a8e-d3b4d202febf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300137741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1300137741
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3005578133
Short name T434
Test name
Test status
Simulation time 1225534042 ps
CPU time 5.88 seconds
Started Jul 29 05:03:04 PM PDT 24
Finished Jul 29 05:03:09 PM PDT 24
Peak memory 221600 kb
Host smart-4b110f1a-1983-4b8a-8177-a24795be0a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005578133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3005578133
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3045640984
Short name T229
Test name
Test status
Simulation time 244574661 ps
CPU time 1.12 seconds
Started Jul 29 05:03:09 PM PDT 24
Finished Jul 29 05:03:10 PM PDT 24
Peak memory 217348 kb
Host smart-f3faad05-6bee-4ea3-a17c-c399dc8a0344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045640984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3045640984
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3816920745
Short name T318
Test name
Test status
Simulation time 118862384 ps
CPU time 0.82 seconds
Started Jul 29 05:03:05 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 200072 kb
Host smart-4ec05ae2-9e7a-4ca6-90b3-3c66d68915a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816920745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3816920745
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.521523875
Short name T27
Test name
Test status
Simulation time 1301952766 ps
CPU time 5 seconds
Started Jul 29 05:03:05 PM PDT 24
Finished Jul 29 05:03:11 PM PDT 24
Peak memory 200472 kb
Host smart-b1edbdcc-3acc-4c0b-837b-de2d53d24ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521523875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.521523875
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4135278783
Short name T332
Test name
Test status
Simulation time 150148231 ps
CPU time 1.15 seconds
Started Jul 29 05:03:07 PM PDT 24
Finished Jul 29 05:03:08 PM PDT 24
Peak memory 200212 kb
Host smart-ffd4f96d-4e47-4c62-93ee-e0cde689181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135278783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4135278783
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2471528219
Short name T164
Test name
Test status
Simulation time 119994608 ps
CPU time 1.25 seconds
Started Jul 29 05:03:07 PM PDT 24
Finished Jul 29 05:03:08 PM PDT 24
Peak memory 200344 kb
Host smart-3fb70433-9fbc-43ff-9db9-d7c6e74d2cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471528219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2471528219
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.734079711
Short name T246
Test name
Test status
Simulation time 4485528108 ps
CPU time 20.45 seconds
Started Jul 29 05:03:10 PM PDT 24
Finished Jul 29 05:03:31 PM PDT 24
Peak memory 200548 kb
Host smart-de7f62cc-ed74-4da0-97d2-f5dc7b7bf894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734079711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.734079711
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.742213612
Short name T478
Test name
Test status
Simulation time 530083101 ps
CPU time 2.9 seconds
Started Jul 29 05:03:04 PM PDT 24
Finished Jul 29 05:03:07 PM PDT 24
Peak memory 200220 kb
Host smart-d07531e6-c4ba-4ea6-aea0-916b9c0bc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742213612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.742213612
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.135191575
Short name T378
Test name
Test status
Simulation time 207566900 ps
CPU time 1.43 seconds
Started Jul 29 05:03:04 PM PDT 24
Finished Jul 29 05:03:06 PM PDT 24
Peak memory 200328 kb
Host smart-6597297b-77ff-44a8-9992-5b360ba16dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135191575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.135191575
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.20513443
Short name T160
Test name
Test status
Simulation time 83855355 ps
CPU time 0.82 seconds
Started Jul 29 05:03:14 PM PDT 24
Finished Jul 29 05:03:15 PM PDT 24
Peak memory 199752 kb
Host smart-83573649-feea-40ae-aae5-bf11d5959da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20513443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.20513443
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3507309234
Short name T455
Test name
Test status
Simulation time 1885376540 ps
CPU time 7.68 seconds
Started Jul 29 05:03:13 PM PDT 24
Finished Jul 29 05:03:21 PM PDT 24
Peak memory 217240 kb
Host smart-090e99d1-7dbc-48ad-a90f-555f6f0bff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507309234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3507309234
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3072606853
Short name T26
Test name
Test status
Simulation time 244614616 ps
CPU time 1.07 seconds
Started Jul 29 05:03:12 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 217436 kb
Host smart-8d341507-b7bf-4407-ac77-d941699e4e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072606853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3072606853
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1889710461
Short name T531
Test name
Test status
Simulation time 235865667 ps
CPU time 1.09 seconds
Started Jul 29 05:03:03 PM PDT 24
Finished Jul 29 05:03:04 PM PDT 24
Peak memory 200316 kb
Host smart-c9b3d216-e345-4b9d-b370-68be8a68d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889710461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1889710461
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.281071241
Short name T104
Test name
Test status
Simulation time 900161323 ps
CPU time 4.42 seconds
Started Jul 29 05:03:06 PM PDT 24
Finished Jul 29 05:03:11 PM PDT 24
Peak memory 200444 kb
Host smart-b4857f30-cd1d-4a3f-9328-ed1d3221d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281071241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.281071241
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3428025784
Short name T165
Test name
Test status
Simulation time 152983354 ps
CPU time 1.07 seconds
Started Jul 29 05:03:13 PM PDT 24
Finished Jul 29 05:03:15 PM PDT 24
Peak memory 200232 kb
Host smart-140fe7dc-37f2-42fc-937f-b63e383189c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428025784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3428025784
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.230261756
Short name T259
Test name
Test status
Simulation time 198403429 ps
CPU time 1.5 seconds
Started Jul 29 05:03:10 PM PDT 24
Finished Jul 29 05:03:12 PM PDT 24
Peak memory 200460 kb
Host smart-2a2856b9-b93b-4cca-b32f-2cfe02cf3b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230261756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.230261756
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.344305998
Short name T360
Test name
Test status
Simulation time 10137983410 ps
CPU time 37.18 seconds
Started Jul 29 05:03:14 PM PDT 24
Finished Jul 29 05:03:51 PM PDT 24
Peak memory 200536 kb
Host smart-b40a6ad4-0359-4d2b-b621-3431b6507422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344305998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.344305998
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2916485959
Short name T3
Test name
Test status
Simulation time 306745064 ps
CPU time 2.28 seconds
Started Jul 29 05:03:14 PM PDT 24
Finished Jul 29 05:03:17 PM PDT 24
Peak memory 200148 kb
Host smart-d329ff74-486d-4a77-b781-324d6b7be317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916485959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2916485959
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1727091447
Short name T249
Test name
Test status
Simulation time 144195775 ps
CPU time 1.09 seconds
Started Jul 29 05:03:07 PM PDT 24
Finished Jul 29 05:03:08 PM PDT 24
Peak memory 200156 kb
Host smart-39e4e813-21f1-490e-a3c8-a1af3317dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727091447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1727091447
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2032977360
Short name T289
Test name
Test status
Simulation time 75373995 ps
CPU time 0.79 seconds
Started Jul 29 05:03:14 PM PDT 24
Finished Jul 29 05:03:15 PM PDT 24
Peak memory 200084 kb
Host smart-b30dddab-fb46-4519-82ce-6314d4c904bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032977360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2032977360
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3052444738
Short name T66
Test name
Test status
Simulation time 1878923111 ps
CPU time 6.5 seconds
Started Jul 29 05:03:11 PM PDT 24
Finished Jul 29 05:03:18 PM PDT 24
Peak memory 221628 kb
Host smart-a1d3940a-f1ec-4f73-8a41-2e25c048ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052444738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3052444738
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1410462918
Short name T394
Test name
Test status
Simulation time 244077496 ps
CPU time 1.15 seconds
Started Jul 29 05:03:14 PM PDT 24
Finished Jul 29 05:03:16 PM PDT 24
Peak memory 217112 kb
Host smart-2ea20563-5fd6-4b98-bee6-19e423be9c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410462918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1410462918
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.247893970
Short name T222
Test name
Test status
Simulation time 86732952 ps
CPU time 0.75 seconds
Started Jul 29 05:03:13 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 200072 kb
Host smart-26b12f1a-37ce-4f81-bc9a-bf518106c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247893970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.247893970
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.984618418
Short name T10
Test name
Test status
Simulation time 1512677122 ps
CPU time 6.12 seconds
Started Jul 29 05:03:15 PM PDT 24
Finished Jul 29 05:03:22 PM PDT 24
Peak memory 200480 kb
Host smart-aee1aa27-9987-413a-8bb4-b8420165b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984618418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.984618418
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4002201987
Short name T507
Test name
Test status
Simulation time 187783395 ps
CPU time 1.27 seconds
Started Jul 29 05:03:12 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 200288 kb
Host smart-379c8e0e-ac81-45e3-94cd-752d786e0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002201987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4002201987
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1750200134
Short name T179
Test name
Test status
Simulation time 256695508 ps
CPU time 1.47 seconds
Started Jul 29 05:03:12 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 200356 kb
Host smart-d0364723-7387-4693-85ab-84e57b0a471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750200134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1750200134
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.394433845
Short name T106
Test name
Test status
Simulation time 8131919267 ps
CPU time 28.03 seconds
Started Jul 29 05:03:16 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 200552 kb
Host smart-0f2b9667-2844-4325-a404-a0906b2e799e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394433845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.394433845
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2381076926
Short name T490
Test name
Test status
Simulation time 124576610 ps
CPU time 1.5 seconds
Started Jul 29 05:03:11 PM PDT 24
Finished Jul 29 05:03:12 PM PDT 24
Peak memory 200124 kb
Host smart-163713b2-337e-448b-83c8-0c80cc3cd1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381076926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2381076926
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1849273012
Short name T375
Test name
Test status
Simulation time 120412806 ps
CPU time 1.01 seconds
Started Jul 29 05:03:11 PM PDT 24
Finished Jul 29 05:03:12 PM PDT 24
Peak memory 200160 kb
Host smart-478f1a0d-6f53-4592-9241-7bbce77f172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849273012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1849273012
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3765182301
Short name T499
Test name
Test status
Simulation time 83290822 ps
CPU time 0.79 seconds
Started Jul 29 05:00:45 PM PDT 24
Finished Jul 29 05:00:46 PM PDT 24
Peak memory 199988 kb
Host smart-e43b38ab-b9bd-4fdc-9055-6844dc5696fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765182301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3765182301
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3027453224
Short name T390
Test name
Test status
Simulation time 1899714144 ps
CPU time 7.52 seconds
Started Jul 29 05:00:44 PM PDT 24
Finished Jul 29 05:00:52 PM PDT 24
Peak memory 217388 kb
Host smart-2b74ec59-9343-4356-9223-cd23c800724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027453224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3027453224
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3474050455
Short name T269
Test name
Test status
Simulation time 244156599 ps
CPU time 1.13 seconds
Started Jul 29 05:00:47 PM PDT 24
Finished Jul 29 05:00:48 PM PDT 24
Peak memory 217364 kb
Host smart-55dc6f6d-3cc0-46ba-94bd-7e42b364388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474050455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3474050455
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2132786647
Short name T302
Test name
Test status
Simulation time 139067118 ps
CPU time 0.82 seconds
Started Jul 29 05:00:35 PM PDT 24
Finished Jul 29 05:00:36 PM PDT 24
Peak memory 199964 kb
Host smart-e61bee11-cec2-4b9f-aee9-e76bc674a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132786647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2132786647
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1762960256
Short name T351
Test name
Test status
Simulation time 1395167394 ps
CPU time 5.62 seconds
Started Jul 29 05:00:38 PM PDT 24
Finished Jul 29 05:00:44 PM PDT 24
Peak memory 200508 kb
Host smart-4e6e8862-61ea-465b-a62f-9374a0fed343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762960256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1762960256
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.660891610
Short name T40
Test name
Test status
Simulation time 133697119 ps
CPU time 1.15 seconds
Started Jul 29 05:00:44 PM PDT 24
Finished Jul 29 05:00:45 PM PDT 24
Peak memory 200272 kb
Host smart-84dbfc3e-6c70-47b4-b95e-f20b80f9a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660891610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.660891610
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4077608319
Short name T505
Test name
Test status
Simulation time 245952958 ps
CPU time 1.47 seconds
Started Jul 29 05:00:34 PM PDT 24
Finished Jul 29 05:00:36 PM PDT 24
Peak memory 200312 kb
Host smart-10070150-bea0-486c-abb0-84978cc0ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077608319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4077608319
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2920499506
Short name T388
Test name
Test status
Simulation time 3499733560 ps
CPU time 12.6 seconds
Started Jul 29 05:00:49 PM PDT 24
Finished Jul 29 05:01:02 PM PDT 24
Peak memory 200444 kb
Host smart-d6ee167f-d9f4-458b-b349-2984ccfed1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920499506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2920499506
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.501089628
Short name T431
Test name
Test status
Simulation time 442900788 ps
CPU time 2.57 seconds
Started Jul 29 05:00:39 PM PDT 24
Finished Jul 29 05:00:41 PM PDT 24
Peak memory 208280 kb
Host smart-d03ece4f-4765-4d19-a9dc-1f299f538aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501089628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.501089628
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2901389591
Short name T339
Test name
Test status
Simulation time 101908874 ps
CPU time 0.94 seconds
Started Jul 29 05:00:37 PM PDT 24
Finished Jul 29 05:00:38 PM PDT 24
Peak memory 200256 kb
Host smart-2fc08516-f447-4fc2-83fa-9a5256ef9cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901389591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2901389591
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.665646962
Short name T330
Test name
Test status
Simulation time 60402587 ps
CPU time 0.71 seconds
Started Jul 29 05:00:44 PM PDT 24
Finished Jul 29 05:00:45 PM PDT 24
Peak memory 199976 kb
Host smart-8ddcc734-861f-44bf-8137-bb383e68d827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665646962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.665646962
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2948691427
Short name T413
Test name
Test status
Simulation time 1225173670 ps
CPU time 5.4 seconds
Started Jul 29 05:00:45 PM PDT 24
Finished Jul 29 05:00:50 PM PDT 24
Peak memory 217136 kb
Host smart-6e973449-b3bf-4ec7-a9e2-c7834f68b94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948691427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2948691427
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1050780032
Short name T153
Test name
Test status
Simulation time 243781553 ps
CPU time 1.13 seconds
Started Jul 29 05:00:42 PM PDT 24
Finished Jul 29 05:00:44 PM PDT 24
Peak memory 217364 kb
Host smart-12411534-27a6-45a7-b0d0-9a818190504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050780032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1050780032
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1179433264
Short name T503
Test name
Test status
Simulation time 168953596 ps
CPU time 0.83 seconds
Started Jul 29 05:00:46 PM PDT 24
Finished Jul 29 05:00:47 PM PDT 24
Peak memory 199972 kb
Host smart-5c2b3c5d-549d-4bbb-b83c-f912f374ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179433264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1179433264
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1028793479
Short name T200
Test name
Test status
Simulation time 1302085998 ps
CPU time 5.15 seconds
Started Jul 29 05:00:46 PM PDT 24
Finished Jul 29 05:00:51 PM PDT 24
Peak memory 200368 kb
Host smart-ce985106-cf1b-45a6-9c4e-b4ec912688b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028793479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1028793479
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3160213849
Short name T281
Test name
Test status
Simulation time 187120278 ps
CPU time 1.2 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 200244 kb
Host smart-b122c35b-58ec-4fbc-b3c9-ba90b3c44e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160213849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3160213849
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.547630381
Short name T54
Test name
Test status
Simulation time 234912884 ps
CPU time 1.5 seconds
Started Jul 29 05:00:46 PM PDT 24
Finished Jul 29 05:00:47 PM PDT 24
Peak memory 200340 kb
Host smart-dbf72190-28ec-490b-aea0-7e0b27fc2d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547630381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.547630381
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.577261906
Short name T396
Test name
Test status
Simulation time 3918683051 ps
CPU time 17.61 seconds
Started Jul 29 05:00:43 PM PDT 24
Finished Jul 29 05:01:01 PM PDT 24
Peak memory 200440 kb
Host smart-b8b533d4-8f28-4888-aab8-6d8e35a223f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577261906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.577261906
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.178651150
Short name T216
Test name
Test status
Simulation time 138208497 ps
CPU time 1.9 seconds
Started Jul 29 05:00:44 PM PDT 24
Finished Jul 29 05:00:46 PM PDT 24
Peak memory 200100 kb
Host smart-9e6f5bce-624d-4885-a55f-f0d4e7ef4f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178651150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.178651150
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4169787171
Short name T94
Test name
Test status
Simulation time 273941149 ps
CPU time 1.49 seconds
Started Jul 29 05:00:43 PM PDT 24
Finished Jul 29 05:00:45 PM PDT 24
Peak memory 200164 kb
Host smart-377f5c1c-9015-4f77-961d-8f64e9da50e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169787171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4169787171
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4248962753
Short name T90
Test name
Test status
Simulation time 71654933 ps
CPU time 0.76 seconds
Started Jul 29 05:00:49 PM PDT 24
Finished Jul 29 05:00:50 PM PDT 24
Peak memory 199928 kb
Host smart-f3af346b-95d6-49d4-8899-3864b6843eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248962753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4248962753
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2361935505
Short name T37
Test name
Test status
Simulation time 2364887012 ps
CPU time 9.4 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:57 PM PDT 24
Peak memory 217716 kb
Host smart-6a3ec91f-4246-4cf1-bef2-c78fd4a74867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361935505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2361935505
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3712182788
Short name T462
Test name
Test status
Simulation time 244069048 ps
CPU time 1.12 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 217356 kb
Host smart-cccd333c-944a-4ec6-a03b-cf4da1202442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712182788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3712182788
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3195082461
Short name T427
Test name
Test status
Simulation time 208953932 ps
CPU time 0.89 seconds
Started Jul 29 05:00:44 PM PDT 24
Finished Jul 29 05:00:45 PM PDT 24
Peak memory 199956 kb
Host smart-19f6511e-54c5-4861-b600-10349143968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195082461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3195082461
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.332209348
Short name T53
Test name
Test status
Simulation time 1342834495 ps
CPU time 5.3 seconds
Started Jul 29 05:00:45 PM PDT 24
Finished Jul 29 05:00:51 PM PDT 24
Peak memory 200408 kb
Host smart-3e1dc8f7-ded6-4545-b316-1bad91969415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332209348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.332209348
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2840763953
Short name T163
Test name
Test status
Simulation time 149738225 ps
CPU time 1.11 seconds
Started Jul 29 05:00:47 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 200164 kb
Host smart-0e7aaca1-469c-452e-bf0d-10b2ff2aef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840763953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2840763953
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3193788498
Short name T171
Test name
Test status
Simulation time 261237508 ps
CPU time 1.52 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 200432 kb
Host smart-296226bc-48e4-49d5-ac74-0346623fa8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193788498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3193788498
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.4175267872
Short name T523
Test name
Test status
Simulation time 6377797158 ps
CPU time 31.27 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:01:20 PM PDT 24
Peak memory 216936 kb
Host smart-8296dc70-34e7-4635-acc1-be76f9d0ba73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175267872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4175267872
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3099274278
Short name T279
Test name
Test status
Simulation time 144997882 ps
CPU time 1.84 seconds
Started Jul 29 05:00:46 PM PDT 24
Finished Jul 29 05:00:48 PM PDT 24
Peak memory 200220 kb
Host smart-2bd9e9b5-2dbf-4c3f-abfe-ce419fb123d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099274278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3099274278
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2284780909
Short name T214
Test name
Test status
Simulation time 132900963 ps
CPU time 1.17 seconds
Started Jul 29 05:00:44 PM PDT 24
Finished Jul 29 05:00:46 PM PDT 24
Peak memory 200164 kb
Host smart-7a9e364a-66b2-4fab-8b39-eeeb41cf66ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284780909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2284780909
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1209882061
Short name T525
Test name
Test status
Simulation time 61081139 ps
CPU time 0.72 seconds
Started Jul 29 05:00:49 PM PDT 24
Finished Jul 29 05:00:50 PM PDT 24
Peak memory 199916 kb
Host smart-435d3c52-129e-497b-815e-7e5f025a328a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209882061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1209882061
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.943163875
Short name T32
Test name
Test status
Simulation time 1904509331 ps
CPU time 6.92 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:55 PM PDT 24
Peak memory 217648 kb
Host smart-97007da8-3ab6-4cba-9b9f-77be8167977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943163875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.943163875
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2547010087
Short name T296
Test name
Test status
Simulation time 244401525 ps
CPU time 1.03 seconds
Started Jul 29 05:00:47 PM PDT 24
Finished Jul 29 05:00:48 PM PDT 24
Peak memory 217376 kb
Host smart-f70c469b-2b6c-4966-a05a-98bd049c1916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547010087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2547010087
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1394427951
Short name T445
Test name
Test status
Simulation time 198162565 ps
CPU time 0.88 seconds
Started Jul 29 05:00:46 PM PDT 24
Finished Jul 29 05:00:47 PM PDT 24
Peak memory 199972 kb
Host smart-571cb8d6-3c6b-4c1c-b44b-3792355cf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394427951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1394427951
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.993831037
Short name T60
Test name
Test status
Simulation time 787075337 ps
CPU time 4.14 seconds
Started Jul 29 05:00:47 PM PDT 24
Finished Jul 29 05:00:52 PM PDT 24
Peak memory 200364 kb
Host smart-4d625182-db15-4956-b96a-4fe47bb215f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993831037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.993831037
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2368093642
Short name T502
Test name
Test status
Simulation time 147288500 ps
CPU time 1.22 seconds
Started Jul 29 05:00:49 PM PDT 24
Finished Jul 29 05:00:50 PM PDT 24
Peak memory 200288 kb
Host smart-93f9f445-980d-4cb9-a227-99812bb6aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368093642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2368093642
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3076182706
Short name T403
Test name
Test status
Simulation time 127608701 ps
CPU time 1.26 seconds
Started Jul 29 05:00:47 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 200276 kb
Host smart-308f0e71-6d96-4630-93b2-26826e609b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076182706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3076182706
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.823495347
Short name T196
Test name
Test status
Simulation time 1164837543 ps
CPU time 5.55 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:53 PM PDT 24
Peak memory 208692 kb
Host smart-9a854470-2709-45b7-9d45-45bcc534e1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823495347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.823495347
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2667281054
Short name T353
Test name
Test status
Simulation time 417335334 ps
CPU time 2.33 seconds
Started Jul 29 05:00:47 PM PDT 24
Finished Jul 29 05:00:50 PM PDT 24
Peak memory 200040 kb
Host smart-b57e9486-14d7-4b10-9117-62ab41830f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667281054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2667281054
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.383762641
Short name T435
Test name
Test status
Simulation time 69234586 ps
CPU time 0.79 seconds
Started Jul 29 05:00:48 PM PDT 24
Finished Jul 29 05:00:49 PM PDT 24
Peak memory 200492 kb
Host smart-8b19c5a5-b57a-4c53-8502-b98fe7e2d47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383762641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.383762641
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.888175667
Short name T463
Test name
Test status
Simulation time 63995091 ps
CPU time 0.77 seconds
Started Jul 29 05:01:01 PM PDT 24
Finished Jul 29 05:01:01 PM PDT 24
Peak memory 200080 kb
Host smart-204e6adb-b1e8-488d-bcee-0eb19acfc0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888175667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.888175667
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.670262735
Short name T49
Test name
Test status
Simulation time 1225408859 ps
CPU time 5.45 seconds
Started Jul 29 05:00:53 PM PDT 24
Finished Jul 29 05:00:59 PM PDT 24
Peak memory 217568 kb
Host smart-3a4be697-8465-4cda-b394-f4e53bf1c1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670262735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.670262735
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.812670918
Short name T416
Test name
Test status
Simulation time 243526483 ps
CPU time 1.12 seconds
Started Jul 29 05:00:58 PM PDT 24
Finished Jul 29 05:01:00 PM PDT 24
Peak memory 217416 kb
Host smart-dbd6e38c-1d82-48d7-b508-ecec5c5ceea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812670918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.812670918
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.687556049
Short name T411
Test name
Test status
Simulation time 184953490 ps
CPU time 0.83 seconds
Started Jul 29 05:00:53 PM PDT 24
Finished Jul 29 05:00:54 PM PDT 24
Peak memory 199972 kb
Host smart-b8370a86-9cf7-4664-b30c-9fd8e88b6918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687556049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.687556049
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1485434763
Short name T530
Test name
Test status
Simulation time 651329955 ps
CPU time 3.5 seconds
Started Jul 29 05:00:53 PM PDT 24
Finished Jul 29 05:00:57 PM PDT 24
Peak memory 200368 kb
Host smart-05368c51-b93c-4d76-8f0d-e018e1e56288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485434763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1485434763
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1396290204
Short name T451
Test name
Test status
Simulation time 117860521 ps
CPU time 1.08 seconds
Started Jul 29 05:00:53 PM PDT 24
Finished Jul 29 05:00:54 PM PDT 24
Peak memory 200120 kb
Host smart-f9bc27c8-981d-4e66-97f7-78ac641a602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396290204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1396290204
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2915308182
Short name T173
Test name
Test status
Simulation time 226906060 ps
CPU time 1.42 seconds
Started Jul 29 05:00:49 PM PDT 24
Finished Jul 29 05:00:51 PM PDT 24
Peak memory 200304 kb
Host smart-3a821aa7-93c3-433e-8b64-49dbe471d046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915308182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2915308182
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2282315536
Short name T438
Test name
Test status
Simulation time 10401746803 ps
CPU time 34.73 seconds
Started Jul 29 05:01:00 PM PDT 24
Finished Jul 29 05:01:35 PM PDT 24
Peak memory 200336 kb
Host smart-669053ad-4c37-4172-95d0-db0dfc6f4dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282315536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2282315536
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4013471251
Short name T389
Test name
Test status
Simulation time 385107849 ps
CPU time 2.58 seconds
Started Jul 29 05:00:53 PM PDT 24
Finished Jul 29 05:00:56 PM PDT 24
Peak memory 200284 kb
Host smart-c8a6c637-ab77-457d-998f-d8ac8b125ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013471251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4013471251
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1358116530
Short name T183
Test name
Test status
Simulation time 182236895 ps
CPU time 1.22 seconds
Started Jul 29 05:00:55 PM PDT 24
Finished Jul 29 05:00:56 PM PDT 24
Peak memory 200240 kb
Host smart-b1b611b5-38ae-4462-aa3e-506e1e3710cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358116530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1358116530
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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