Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	660190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

395134

1

T1

1224

T3

1128

T4

12018

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	564698	1			T1	1869		T2	20		T3	1500
values[0x0]	245169	1			T1	668		T3	827		T4	7099
values[0x1]	245457	1			T1	668		T3	873		T4	6939

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	554097	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

501227

1

T1

1576

T2

8

T3

1470

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4403	1			T1	13		T3	13		T4	101
valid_sources[0x01]	6624	1			T1	14		T3	17		T4	101
valid_sources[0x02]	3908	1			T1	9		T3	16		T4	149
valid_sources[0x03]	4050	1			T1	20		T3	5		T4	131
valid_sources[0x04]	4554	1			T1	14		T2	1		T3	17
valid_sources[0x05]	4550	1			T1	18		T3	9		T4	133
valid_sources[0x06]	3622	1			T1	20		T3	7		T4	112
valid_sources[0x07]	6351	1			T1	8		T3	9		T4	130
valid_sources[0x08]	3738	1			T1	19		T3	5		T4	133
valid_sources[0x09]	3693	1			T1	12		T3	12		T4	103
valid_sources[0x0a]	3989	1			T1	5		T3	10		T4	172
valid_sources[0x0b]	4305	1			T1	11		T3	4		T4	108
valid_sources[0x0c]	4342	1			T1	9		T3	19		T4	101
valid_sources[0x0d]	3805	1			T1	10		T3	13		T4	142
valid_sources[0x0e]	3404	1			T1	15		T3	11		T4	108
valid_sources[0x0f]	3402	1			T1	13		T3	14		T4	123
valid_sources[0x10]	7359	1			T1	11		T2	1		T3	14
valid_sources[0x11]	4609	1			T1	7		T3	14		T4	137
valid_sources[0x12]	4168	1			T1	9		T3	17		T4	142
valid_sources[0x13]	6977	1			T1	12		T3	11		T4	145
valid_sources[0x14]	4278	1			T1	8		T3	14		T4	110
valid_sources[0x15]	3768	1			T1	16		T3	10		T4	146
valid_sources[0x16]	3655	1			T1	22		T3	17		T4	131
valid_sources[0x17]	3861	1			T1	9		T3	15		T4	116
valid_sources[0x18]	3835	1			T1	15		T3	20		T4	151
valid_sources[0x19]	4815	1			T1	9		T3	11		T4	130
valid_sources[0x1a]	3964	1			T1	18		T3	14		T4	80
valid_sources[0x1b]	3555	1			T1	13		T3	14		T4	105
valid_sources[0x1c]	3229	1			T1	8		T3	15		T4	118
valid_sources[0x1d]	4353	1			T1	13		T2	3		T3	6
valid_sources[0x1e]	4635	1			T1	19		T3	9		T4	136
valid_sources[0x1f]	5148	1			T1	13		T3	14		T4	128
valid_sources[0x20]	4482	1			T1	9		T3	6		T4	146
valid_sources[0x21]	4141	1			T1	9		T3	22		T4	172
valid_sources[0x22]	4453	1			T1	14		T3	16		T4	96
valid_sources[0x23]	3422	1			T1	12		T3	18		T4	147
valid_sources[0x24]	3617	1			T1	12		T3	16		T4	107
valid_sources[0x25]	4654	1			T1	18		T3	10		T4	93
valid_sources[0x26]	3623	1			T1	12		T3	17		T4	137
valid_sources[0x27]	5885	1			T1	15		T3	10		T4	95
valid_sources[0x28]	3121	1			T1	10		T3	5		T4	146
valid_sources[0x29]	3544	1			T1	19		T3	21		T4	135
valid_sources[0x2a]	3539	1			T1	13		T3	8		T4	157
valid_sources[0x2b]	4521	1			T1	14		T3	9		T4	134
valid_sources[0x2c]	3908	1			T1	8		T3	7		T4	181
valid_sources[0x2d]	3578	1			T1	8		T3	16		T4	153
valid_sources[0x2e]	4421	1			T1	12		T3	16		T4	91
valid_sources[0x2f]	3493	1			T1	12		T3	11		T4	105
valid_sources[0x30]	3792	1			T1	16		T2	1		T3	16
valid_sources[0x31]	4319	1			T1	9		T3	9		T4	132
valid_sources[0x32]	3229	1			T1	10		T3	13		T4	95
valid_sources[0x33]	4060	1			T1	19		T3	16		T4	151
valid_sources[0x34]	4214	1			T1	15		T3	12		T4	112
valid_sources[0x35]	5321	1			T1	10		T3	11		T4	104
valid_sources[0x36]	4719	1			T1	12		T3	9		T4	125
valid_sources[0x37]	5666	1			T1	17		T3	20		T4	110
valid_sources[0x38]	3637	1			T1	12		T3	11		T4	117
valid_sources[0x39]	3674	1			T1	11		T3	11		T4	132
valid_sources[0x3a]	3470	1			T1	12		T3	14		T4	159
valid_sources[0x3b]	3771	1			T1	14		T3	11		T4	143
valid_sources[0x3c]	7214	1			T1	6		T3	12		T4	137
valid_sources[0x3d]	4121	1			T1	6		T2	1		T3	16
valid_sources[0x3e]	2946	1			T1	10		T3	22		T4	141
valid_sources[0x3f]	3911	1			T1	5		T3	19		T4	112
valid_sources[0x40]	3706	1			T1	12		T3	12		T4	121
valid_sources[0x41]	3390	1			T1	12		T2	1		T3	14
valid_sources[0x42]	4215	1			T1	15		T3	14		T4	121
valid_sources[0x43]	4716	1			T1	14		T3	8		T4	85
valid_sources[0x44]	4557	1			T1	6		T2	1		T3	19
valid_sources[0x45]	7846	1			T1	15		T3	13		T4	156
valid_sources[0x46]	3909	1			T1	14		T3	10		T4	110
valid_sources[0x47]	3672	1			T1	15		T3	21		T4	138
valid_sources[0x48]	3766	1			T1	17		T3	14		T4	99
valid_sources[0x49]	3299	1			T1	15		T3	13		T4	103
valid_sources[0x4a]	4258	1			T1	11		T3	13		T4	114
valid_sources[0x4b]	3702	1			T1	9		T3	14		T4	77
valid_sources[0x4c]	3623	1			T1	14		T3	13		T4	135
valid_sources[0x4d]	3239	1			T1	9		T3	9		T4	98
valid_sources[0x4e]	3519	1			T1	6		T3	19		T4	116
valid_sources[0x4f]	3475	1			T1	10		T3	5		T4	118
valid_sources[0x50]	4044	1			T1	10		T3	13		T4	107
valid_sources[0x51]	3573	1			T1	6		T3	13		T4	109
valid_sources[0x52]	3890	1			T1	19		T3	12		T4	137
valid_sources[0x53]	4093	1			T1	12		T3	19		T4	155
valid_sources[0x54]	3062	1			T1	9		T3	8		T4	107
valid_sources[0x55]	4116	1			T1	17		T3	17		T4	109
valid_sources[0x56]	4297	1			T1	11		T3	16		T4	169
valid_sources[0x57]	4133	1			T1	8		T3	8		T4	121
valid_sources[0x58]	3482	1			T1	10		T3	16		T4	110
valid_sources[0x59]	4281	1			T1	12		T3	6		T4	73
valid_sources[0x5a]	4232	1			T1	13		T3	13		T4	127
valid_sources[0x5b]	5259	1			T1	14		T3	18		T4	131
valid_sources[0x5c]	4079	1			T1	15		T3	11		T4	146
valid_sources[0x5d]	4499	1			T1	12		T3	13		T4	138
valid_sources[0x5e]	4280	1			T1	10		T3	10		T4	120
valid_sources[0x5f]	4268	1			T1	10		T3	14		T4	141
valid_sources[0x60]	3674	1			T1	6		T3	15		T4	104
valid_sources[0x61]	4042	1			T1	16		T3	20		T4	151
valid_sources[0x62]	3624	1			T1	11		T3	7		T4	113
valid_sources[0x63]	3485	1			T1	9		T3	11		T4	97
valid_sources[0x64]	3415	1			T1	11		T3	14		T4	109
valid_sources[0x65]	3766	1			T1	15		T3	16		T4	142
valid_sources[0x66]	3543	1			T1	10		T3	9		T4	111
valid_sources[0x67]	3313	1			T1	11		T3	15		T4	107
valid_sources[0x68]	3616	1			T1	10		T2	1		T3	12
valid_sources[0x69]	3285	1			T1	16		T2	2		T3	9
valid_sources[0x6a]	6185	1			T1	9		T3	12		T4	151
valid_sources[0x6b]	3245	1			T1	10		T3	10		T4	70
valid_sources[0x6c]	3518	1			T1	12		T3	17		T4	132
valid_sources[0x6d]	3467	1			T1	9		T3	10		T4	105
valid_sources[0x6e]	3371	1			T1	15		T3	13		T4	141
valid_sources[0x6f]	3740	1			T1	14		T3	9		T4	128
valid_sources[0x70]	4251	1			T1	11		T3	12		T4	116
valid_sources[0x71]	4484	1			T1	7		T3	11		T4	77
valid_sources[0x72]	3485	1			T1	8		T3	9		T4	116
valid_sources[0x73]	8387	1			T1	19		T3	8		T4	130
valid_sources[0x74]	3540	1			T1	12		T3	7		T4	121
valid_sources[0x75]	4838	1			T1	8		T3	9		T4	167
valid_sources[0x76]	3409	1			T1	5		T3	11		T4	124
valid_sources[0x77]	3544	1			T1	14		T3	11		T4	97
valid_sources[0x78]	4968	1			T1	19		T3	14		T4	145
valid_sources[0x79]	3815	1			T1	21		T3	14		T4	168
valid_sources[0x7a]	3687	1			T1	15		T3	8		T4	105
valid_sources[0x7b]	3741	1			T1	11		T3	14		T4	139
valid_sources[0x7c]	3240	1			T1	12		T3	16		T4	162
valid_sources[0x7d]	3984	1			T1	11		T3	13		T4	109
valid_sources[0x7e]	6007	1			T1	9		T3	13		T4	101
valid_sources[0x7f]	3026	1			T1	14		T3	18		T4	164
valid_sources[0x80]	4485	1			T1	5		T3	20		T4	143

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

264526

1

T1

883

T3

715

T4

8426

values[0x0]

all_enables

biggest_size

85267

1

T1

218

T3

267

T4

2441

values[0x1]

all_enables

biggest_size

45341

1

T1

123

T3

146

T4

1151