Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T8
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T4,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	59542998	9394	0	0
CascadeEffAonToRstPorAboveRise_A	59542998	9394	0	0
CascadeEffAonToRstPorIoAboveFall_A	57159588	9394	0	0
CascadeEffAonToRstPorIoAboveRise_A	57159588	9394	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	28580875	9394	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	28580875	9394	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14290117	9394	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14290117	9394	0	0
CascadeEffAonToRstPorUcbAboveFall_A	28581012	9394	0	0
CascadeEffAonToRstPorUcbAboveRise_A	28581012	9394	0	0
CascadeLcToLcAboveFall_A	59542998	23380	0	0
CascadeLcToLcAboveRise_A	59542998	23380	0	0
CascadeLcToLcAonAboveFall_A	1804680	23380	0	0
CascadeLcToLcAonAboveRise_A	1804680	23380	0	0
CascadeLcToLcShadowedAboveFall_A	59542998	23380	0	0
CascadeLcToLcShadowedAboveRise_A	59542998	23380	0	0
CascadePorToAonAboveFall_A	1804680	7239	0	0
CascadeSysToSysAboveFall_A	59542998	23380	0	0
CascadeSysToSysAboveRise_A	59542998	23380	0	0
ScanRstToAonRise_A	1804680	236	0	0
StablePorToAonRise_A	1804680	9394	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12705255	23380	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12705255	23380	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12705255	23380	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12705255	23380	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14290117	23380	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14290117	23380	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12705255	23380	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12705255	23380	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12705255	23380	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12705255	23380	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	9394	0	0
T1	172386	26	0	0
T2	164360	541	0	0
T3	121828	27	0	0
T4	168714	224	0	0
T5	16330	2	0	0
T6	22339	1	0	0
T7	25643	1	0	0
T8	10258	2	0	0
T9	748200	91	0	0
T10	17054	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	9394	0	0
T1	172386	26	0	0
T2	164360	541	0	0
T3	121828	27	0	0
T4	168714	224	0	0
T5	16330	2	0	0
T6	22339	1	0	0
T7	25643	1	0	0
T8	10258	2	0	0
T9	748200	91	0	0
T10	17054	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57159588	9394	0	0
T1	165501	26	0	0
T2	157782	541	0	0
T3	116981	27	0	0
T4	161962	224	0	0
T5	15676	2	0	0
T6	21444	1	0	0
T7	24616	1	0	0
T8	9851	2	0	0
T9	718254	91	0	0
T10	16372	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57159588	9394	0	0
T1	165501	26	0	0
T2	157782	541	0	0
T3	116981	27	0	0
T4	161962	224	0	0
T5	15676	2	0	0
T6	21444	1	0	0
T7	24616	1	0	0
T8	9851	2	0	0
T9	718254	91	0	0
T10	16372	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28580875	9394	0	0
T1	82750	26	0	0
T2	788919	541	0	0
T3	58488	27	0	0
T4	809857	224	0	0
T5	7838	2	0	0
T6	10722	1	0	0
T7	12307	1	0	0
T8	4927	2	0	0
T9	359136	91	0	0
T10	8186	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28580875	9394	0	0
T1	82750	26	0	0
T2	788919	541	0	0
T3	58488	27	0	0
T4	809857	224	0	0
T5	7838	2	0	0
T6	10722	1	0	0
T7	12307	1	0	0
T8	4927	2	0	0
T9	359136	91	0	0
T10	8186	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	9394	0	0
T1	41370	26	0	0
T2	394411	541	0	0
T3	29243	27	0	0
T4	404936	224	0	0
T5	3918	2	0	0
T6	5360	1	0	0
T7	6153	1	0	0
T8	2461	2	0	0
T9	179571	91	0	0
T10	4093	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	9394	0	0
T1	41370	26	0	0
T2	394411	541	0	0
T3	29243	27	0	0
T4	404936	224	0	0
T5	3918	2	0	0
T6	5360	1	0	0
T7	6153	1	0	0
T8	2461	2	0	0
T9	179571	91	0	0
T10	4093	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28581012	9394	0	0
T1	82747	26	0	0
T2	788980	541	0	0
T3	58489	27	0	0
T4	809866	224	0	0
T5	7839	2	0	0
T6	10722	1	0	0
T7	12308	1	0	0
T8	4927	2	0	0
T9	359151	91	0	0
T10	8186	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28581012	9394	0	0
T1	82747	26	0	0
T2	788980	541	0	0
T3	58489	27	0	0
T4	809866	224	0	0
T5	7839	2	0	0
T6	10722	1	0	0
T7	12308	1	0	0
T8	4927	2	0	0
T9	359151	91	0	0
T10	8186	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	23380	0	0
T1	172386	60	0	0
T2	164360	541	0	0
T3	121828	102	0	0
T4	168714	605	0	0
T5	16330	2	0	0
T6	22339	15	0	0
T7	25643	1	0	0
T8	10258	6	0	0
T9	748200	276	0	0
T10	17054	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	23380	0	0
T1	172386	60	0	0
T2	164360	541	0	0
T3	121828	102	0	0
T4	168714	605	0	0
T5	16330	2	0	0
T6	22339	15	0	0
T7	25643	1	0	0
T8	10258	6	0	0
T9	748200	276	0	0
T10	17054	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	23380	0	0
T1	5233	60	0	0
T2	49554	541	0	0
T3	3669	102	0	0
T4	51364	605	0	0
T5	488	2	0	0
T6	669	15	0	0
T7	768	1	0	0
T8	307	6	0	0
T9	22750	276	0	0
T10	510	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	23380	0	0
T1	5233	60	0	0
T2	49554	541	0	0
T3	3669	102	0	0
T4	51364	605	0	0
T5	488	2	0	0
T6	669	15	0	0
T7	768	1	0	0
T8	307	6	0	0
T9	22750	276	0	0
T10	510	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	23380	0	0
T1	172386	60	0	0
T2	164360	541	0	0
T3	121828	102	0	0
T4	168714	605	0	0
T5	16330	2	0	0
T6	22339	15	0	0
T7	25643	1	0	0
T8	10258	6	0	0
T9	748200	276	0	0
T10	17054	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	23380	0	0
T1	172386	60	0	0
T2	164360	541	0	0
T3	121828	102	0	0
T4	168714	605	0	0
T5	16330	2	0	0
T6	22339	15	0	0
T7	25643	1	0	0
T8	10258	6	0	0
T9	748200	276	0	0
T10	17054	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	7239	0	0
T1	5233	11	0	0
T2	49554	541	0	0
T3	3669	27	0	0
T4	51364	116	0	0
T5	488	11	0	0
T6	669	1	0	0
T7	768	1	0	0
T8	307	1	0	0
T9	22750	48	0	0
T10	510	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	23380	0	0
T1	172386	60	0	0
T2	164360	541	0	0
T3	121828	102	0	0
T4	168714	605	0	0
T5	16330	2	0	0
T6	22339	15	0	0
T7	25643	1	0	0
T8	10258	6	0	0
T9	748200	276	0	0
T10	17054	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59542998	23380	0	0
T1	172386	60	0	0
T2	164360	541	0	0
T3	121828	102	0	0
T4	168714	605	0	0
T5	16330	2	0	0
T6	22339	15	0	0
T7	25643	1	0	0
T8	10258	6	0	0
T9	748200	276	0	0
T10	17054	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	236	0	0
T1	5233	1	0	0
T2	49554	0	0	0
T3	3669	0	0	0
T4	51364	10	0	0
T5	488	0	0	0
T6	669	0	0	0
T7	768	0	0	0
T8	307	0	0	0
T9	22750	2	0	0
T10	510	0	0	0
T37	0	5	0	0
T64	0	2	0	0
T73	0	1	0	0
T74	0	9	0	0
T75	0	2	0	0
T76	0	2	0	0
T83	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	9394	0	0
T1	5233	26	0	0
T2	49554	541	0	0
T3	3669	27	0	0
T4	51364	224	0	0
T5	488	2	0	0
T6	669	1	0	0
T7	768	1	0	0
T8	307	2	0	0
T9	22750	91	0	0
T10	510	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	23380	0	0
T1	41370	60	0	0
T2	394411	541	0	0
T3	29243	102	0	0
T4	404936	605	0	0
T5	3918	2	0	0
T6	5360	15	0	0
T7	6153	1	0	0
T8	2461	6	0	0
T9	179571	276	0	0
T10	4093	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	23380	0	0
T1	41370	60	0	0
T2	394411	541	0	0
T3	29243	102	0	0
T4	404936	605	0	0
T5	3918	2	0	0
T6	5360	15	0	0
T7	6153	1	0	0
T8	2461	6	0	0
T9	179571	276	0	0
T10	4093	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12705255	23380	0	0
T1	35115	60	0	0
T2	383464	541	0	0
T3	26194	102	0	0
T4	351194	605	0	0
T5	3828	2	0	0
T6	4259	15	0	0
T7	6087	1	0	0
T8	2174	6	0	0
T9	156227	276	0	0
T10	3850	6	0	0