Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14290117	14880	0	0
gen_assertions[0].RstEnOn_A	14290117	1080	0	0
gen_assertions[0].RstNOff_A	14290117	14880	0	0
gen_assertions[0].RstNOn_A	14290117	1080	0	0
gen_assertions[1].RstEnOff_A	57159588	13602	0	0
gen_assertions[1].RstEnOn_A	57159588	1037	0	0
gen_assertions[1].RstNOff_A	57159588	13602	0	0
gen_assertions[1].RstNOn_A	57159588	1037	0	0
gen_assertions[2].RstEnOff_A	28580875	13625	0	0
gen_assertions[2].RstEnOn_A	28580875	1039	0	0
gen_assertions[2].RstNOff_A	28580875	13625	0	0
gen_assertions[2].RstNOn_A	28580875	1039	0	0
gen_assertions[3].RstEnOff_A	28581012	13679	0	0
gen_assertions[3].RstEnOn_A	28581012	1075	0	0
gen_assertions[3].RstNOff_A	28581012	13679	0	0
gen_assertions[3].RstNOn_A	28581012	1075	0	0
gen_assertions[4].RstEnOff_A	1804680	23118	0	0
gen_assertions[4].RstEnOn_A	1804680	1122	0	0
gen_assertions[4].RstNOff_A	1804680	23118	0	0
gen_assertions[4].RstNOn_A	1804680	1122	0	0
gen_assertions[5].RstEnOff_A	14290117	15120	0	0
gen_assertions[5].RstEnOn_A	14290117	1175	0	0
gen_assertions[5].RstNOff_A	14290117	15120	0	0
gen_assertions[5].RstNOn_A	14290117	1175	0	0
gen_assertions[6].RstEnOff_A	14290117	15171	0	0
gen_assertions[6].RstEnOn_A	14290117	1230	0	0
gen_assertions[6].RstNOff_A	14290117	15171	0	0
gen_assertions[6].RstNOn_A	14290117	1230	0	0
gen_assertions[7].RstEnOff_A	14290117	15221	0	0
gen_assertions[7].RstEnOn_A	14290117	1269	0	0
gen_assertions[7].RstNOff_A	14290117	15221	0	0
gen_assertions[7].RstNOn_A	14290117	1269	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	14880	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	404	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	0	0	0
T8	2461	4	0	0
T9	179571	196	0	0
T10	4093	4	0	0
T11	0	4	0	0
T13	0	4	0	0
T22	0	42	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1080	0	0
T4	404936	25	0	0
T5	3918	0	0	0
T6	5360	4	0	0
T7	6153	0	0	0
T8	2461	0	0	0
T9	179571	12	0	0
T10	4093	0	0	0
T11	3068	4	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	5	0	0
T23	0	5	0	0
T37	0	13	0	0
T44	0	7	0	0
T47	0	4	0	0
T48	0	7	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	14880	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	404	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	0	0	0
T8	2461	4	0	0
T9	179571	196	0	0
T10	4093	4	0	0
T11	0	4	0	0
T13	0	4	0	0
T22	0	42	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1080	0	0
T4	404936	25	0	0
T5	3918	0	0	0
T6	5360	4	0	0
T7	6153	0	0	0
T8	2461	0	0	0
T9	179571	12	0	0
T10	4093	0	0	0
T11	3068	4	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	5	0	0
T23	0	5	0	0
T37	0	13	0	0
T44	0	7	0	0
T47	0	4	0	0
T48	0	7	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57159588	13602	0	0
T1	165501	32	0	0
T2	157782	0	0	0
T3	116981	68	0	0
T4	161962	359	0	0
T5	15676	0	0	0
T6	21444	13	0	0
T7	24616	2	0	0
T8	9851	4	0	0
T9	718254	171	0	0
T10	16372	4	0	0
T11	0	4	0	0
T13	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57159588	1037	0	0
T4	161962	18	0	0
T5	15676	0	0	0
T6	21444	0	0	0
T7	24616	2	0	0
T8	9851	0	0	0
T9	718254	15	0	0
T10	16372	0	0	0
T11	12274	4	0	0
T12	16439	0	0	0
T13	13652	0	0	0
T22	0	5	0	0
T23	0	3	0	0
T37	0	15	0	0
T44	0	9	0	0
T46	0	3	0	0
T48	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57159588	13602	0	0
T1	165501	32	0	0
T2	157782	0	0	0
T3	116981	68	0	0
T4	161962	359	0	0
T5	15676	0	0	0
T6	21444	13	0	0
T7	24616	2	0	0
T8	9851	4	0	0
T9	718254	171	0	0
T10	16372	4	0	0
T11	0	4	0	0
T13	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57159588	1037	0	0
T4	161962	18	0	0
T5	15676	0	0	0
T6	21444	0	0	0
T7	24616	2	0	0
T8	9851	0	0	0
T9	718254	15	0	0
T10	16372	0	0	0
T11	12274	4	0	0
T12	16439	0	0	0
T13	13652	0	0	0
T22	0	5	0	0
T23	0	3	0	0
T37	0	15	0	0
T44	0	9	0	0
T46	0	3	0	0
T48	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28580875	13625	0	0
T1	82750	32	0	0
T2	788919	0	0	0
T3	58488	68	0	0
T4	809857	366	0	0
T5	7838	0	0	0
T6	10722	13	0	0
T7	12307	3	0	0
T8	4927	4	0	0
T9	359136	170	0	0
T10	8186	4	0	0
T11	0	5	0	0
T13	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28580875	1039	0	0
T4	809857	27	0	0
T5	7838	0	0	0
T6	10722	0	0	0
T7	12307	3	0	0
T8	4927	0	0	0
T9	359136	15	0	0
T10	8186	0	0	0
T11	6137	5	0	0
T12	8220	0	0	0
T13	6826	0	0	0
T22	0	4	0	0
T37	0	19	0	0
T44	0	10	0	0
T46	0	2	0	0
T47	0	6	0	0
T48	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28580875	13625	0	0
T1	82750	32	0	0
T2	788919	0	0	0
T3	58488	68	0	0
T4	809857	366	0	0
T5	7838	0	0	0
T6	10722	13	0	0
T7	12307	3	0	0
T8	4927	4	0	0
T9	359136	170	0	0
T10	8186	4	0	0
T11	0	5	0	0
T13	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28580875	1039	0	0
T4	809857	27	0	0
T5	7838	0	0	0
T6	10722	0	0	0
T7	12307	3	0	0
T8	4927	0	0	0
T9	359136	15	0	0
T10	8186	0	0	0
T11	6137	5	0	0
T12	8220	0	0	0
T13	6826	0	0	0
T22	0	4	0	0
T37	0	19	0	0
T44	0	10	0	0
T46	0	2	0	0
T47	0	6	0	0
T48	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28581012	13679	0	0
T1	82747	32	0	0
T2	788980	0	0	0
T3	58489	68	0	0
T4	809866	367	0	0
T5	7839	0	0	0
T6	10722	13	0	0
T7	12308	4	0	0
T8	4927	4	0	0
T9	359151	171	0	0
T10	8186	4	0	0
T11	0	7	0	0
T13	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28581012	1075	0	0
T4	809866	28	0	0
T5	7839	0	0	0
T6	10722	0	0	0
T7	12308	4	0	0
T8	4927	0	0	0
T9	359151	14	0	0
T10	8186	0	0	0
T11	6136	7	0	0
T12	8220	0	0	0
T13	6825	0	0	0
T22	0	5	0	0
T37	0	14	0	0
T44	0	11	0	0
T46	0	4	0	0
T47	0	6	0	0
T48	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28581012	13679	0	0
T1	82747	32	0	0
T2	788980	0	0	0
T3	58489	68	0	0
T4	809866	367	0	0
T5	7839	0	0	0
T6	10722	13	0	0
T7	12308	4	0	0
T8	4927	4	0	0
T9	359151	171	0	0
T10	8186	4	0	0
T11	0	7	0	0
T13	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28581012	1075	0	0
T4	809866	28	0	0
T5	7839	0	0	0
T6	10722	0	0	0
T7	12308	4	0	0
T8	4927	0	0	0
T9	359151	14	0	0
T10	8186	0	0	0
T11	6136	7	0	0
T12	8220	0	0	0
T13	6825	0	0	0
T22	0	5	0	0
T37	0	14	0	0
T44	0	11	0	0
T46	0	4	0	0
T47	0	6	0	0
T48	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	23118	0	0
T1	5233	60	0	0
T2	49554	541	0	0
T3	3669	75	0	0
T4	51364	623	0	0
T5	488	2	0	0
T6	669	15	0	0
T7	768	6	0	0
T8	307	5	0	0
T9	22750	278	0	0
T10	510	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	1122	0	0
T4	51364	28	0	0
T5	488	0	0	0
T6	669	0	0	0
T7	768	5	0	0
T8	307	0	0	0
T9	22750	12	0	0
T10	510	0	0	0
T11	383	8	0	0
T12	513	0	0	0
T13	425	0	0	0
T22	0	5	0	0
T37	0	16	0	0
T43	0	1	0	0
T44	0	9	0	0
T46	0	6	0	0
T48	0	9	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	23118	0	0
T1	5233	60	0	0
T2	49554	541	0	0
T3	3669	75	0	0
T4	51364	623	0	0
T5	488	2	0	0
T6	669	15	0	0
T7	768	6	0	0
T8	307	5	0	0
T9	22750	278	0	0
T10	510	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804680	1122	0	0
T4	51364	28	0	0
T5	488	0	0	0
T6	669	0	0	0
T7	768	5	0	0
T8	307	0	0	0
T9	22750	12	0	0
T10	510	0	0	0
T11	383	8	0	0
T12	513	0	0	0
T13	425	0	0	0
T22	0	5	0	0
T37	0	16	0	0
T43	0	1	0	0
T44	0	9	0	0
T46	0	6	0	0
T48	0	9	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	15120	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	401	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	6	0	0
T8	2461	4	0	0
T9	179571	199	0	0
T10	4093	4	0	0
T11	0	7	0	0
T13	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1175	0	0
T4	404936	21	0	0
T5	3918	0	0	0
T6	5360	0	0	0
T7	6153	6	0	0
T8	2461	0	0	0
T9	179571	14	0	0
T10	4093	0	0	0
T11	3068	7	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	4	0	0
T37	0	15	0	0
T44	0	10	0	0
T46	0	7	0	0
T47	0	7	0	0
T48	0	10	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	15120	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	401	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	6	0	0
T8	2461	4	0	0
T9	179571	199	0	0
T10	4093	4	0	0
T11	0	7	0	0
T13	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1175	0	0
T4	404936	21	0	0
T5	3918	0	0	0
T6	5360	0	0	0
T7	6153	6	0	0
T8	2461	0	0	0
T9	179571	14	0	0
T10	4093	0	0	0
T11	3068	7	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	4	0	0
T37	0	15	0	0
T44	0	10	0	0
T46	0	7	0	0
T47	0	7	0	0
T48	0	10	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	15171	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	405	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	6	0	0
T8	2461	4	0	0
T9	179571	197	0	0
T10	4093	4	0	0
T11	0	8	0	0
T13	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1230	0	0
T4	404936	27	0	0
T5	3918	0	0	0
T6	5360	0	0	0
T7	6153	6	0	0
T8	2461	0	0	0
T9	179571	13	0	0
T10	4093	0	0	0
T11	3068	8	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	3	0	0
T37	0	11	0	0
T44	0	15	0	0
T46	0	8	0	0
T47	0	10	0	0
T48	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	15171	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	405	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	6	0	0
T8	2461	4	0	0
T9	179571	197	0	0
T10	4093	4	0	0
T11	0	8	0	0
T13	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1230	0	0
T4	404936	27	0	0
T5	3918	0	0	0
T6	5360	0	0	0
T7	6153	6	0	0
T8	2461	0	0	0
T9	179571	13	0	0
T10	4093	0	0	0
T11	3068	8	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	3	0	0
T37	0	11	0	0
T44	0	15	0	0
T46	0	8	0	0
T47	0	10	0	0
T48	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	15221	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	404	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	8	0	0
T8	2461	4	0	0
T9	179571	199	0	0
T10	4093	4	0	0
T11	0	11	0	0
T13	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1269	0	0
T4	404936	24	0	0
T5	3918	0	0	0
T6	5360	0	0	0
T7	6153	8	0	0
T8	2461	0	0	0
T9	179571	16	0	0
T10	4093	0	0	0
T11	3068	11	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	5	0	0
T37	0	17	0	0
T43	0	1	0	0
T44	0	12	0	0
T46	0	8	0	0
T48	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	15221	0	0
T1	41370	34	0	0
T2	394411	0	0	0
T3	29243	75	0	0
T4	404936	404	0	0
T5	3918	0	0	0
T6	5360	14	0	0
T7	6153	8	0	0
T8	2461	4	0	0
T9	179571	199	0	0
T10	4093	4	0	0
T11	0	11	0	0
T13	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14290117	1269	0	0
T4	404936	24	0	0
T5	3918	0	0	0
T6	5360	0	0	0
T7	6153	8	0	0
T8	2461	0	0	0
T9	179571	16	0	0
T10	4093	0	0	0
T11	3068	11	0	0
T12	4109	0	0	0
T13	3413	0	0	0
T22	0	5	0	0
T37	0	17	0	0
T43	0	1	0	0
T44	0	12	0	0
T46	0	8	0	0
T48	0	13	0	0