Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13496882	7301	0	0
alert_regwen_rd_A	13496882	4918	0	0
cpu_regwen_rd_A	13496882	4785	0	0
sw_rst_ctrl_n_0_rd_A	13496882	11272	0	0
sw_rst_ctrl_n_1_rd_A	13496882	11270	0	0
sw_rst_ctrl_n_2_rd_A	13496882	11090	0	0
sw_rst_ctrl_n_3_rd_A	13496882	11107	0	0
sw_rst_ctrl_n_4_rd_A	13496882	11210	0	0
sw_rst_ctrl_n_5_rd_A	13496882	11093	0	0
sw_rst_ctrl_n_6_rd_A	13496882	11226	0	0
sw_rst_ctrl_n_7_rd_A	13496882	11471	0	0
sw_rst_regwen_0_rd_A	13496882	5416	0	0
sw_rst_regwen_1_rd_A	13496882	5379	0	0
sw_rst_regwen_2_rd_A	13496882	5287	0	0
sw_rst_regwen_3_rd_A	13496882	5466	0	0
sw_rst_regwen_4_rd_A	13496882	5181	0	0
sw_rst_regwen_5_rd_A	13496882	5315	0	0
sw_rst_regwen_6_rd_A	13496882	5416	0	0
sw_rst_regwen_7_rd_A	13496882	5510	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	7301	0	0
T51	3782	12	0	0
T53	7233	232	0	0
T54	3811	89	0	0
T55	19562	3	0	0
T56	16310	2	0	0
T61	4917	10	0	0
T66	2986	132	0	0
T67	17449	2	0	0
T68	5199	447	0	0
T69	6236	149	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	4918	0	0
T17	3352	0	0	0
T26	42195	0	0	0
T33	26244	0	0	0
T73	45490	67	0	0
T74	266443	398	0	0
T75	14769	0	0	0
T76	121952	112	0	0
T79	0	271	0	0
T80	0	127	0	0
T81	0	30	0	0
T84	0	55	0	0
T98	0	194	0	0
T99	0	263	0	0
T100	0	83	0	0
T101	2702	0	0	0
T102	2158	0	0	0
T103	2119	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	4785	0	0
T17	3352	0	0	0
T26	42195	0	0	0
T33	26244	0	0	0
T73	45490	99	0	0
T74	266443	380	0	0
T75	14769	0	0	0
T76	121952	112	0	0
T79	0	230	0	0
T80	0	99	0	0
T81	0	17	0	0
T84	0	39	0	0
T98	0	209	0	0
T99	0	248	0	0
T100	0	65	0	0
T101	2702	0	0	0
T102	2158	0	0	0
T103	2119	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11272	0	0
T6	4259	37	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	174	0	0
T73	0	104	0	0
T74	0	680	0	0
T76	0	215	0	0
T79	0	614	0	0
T80	0	388	0	0
T104	0	18	0	0
T105	0	31	0	0
T106	0	64	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11270	0	0
T6	4259	56	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	203	0	0
T73	0	76	0	0
T74	0	713	0	0
T76	0	240	0	0
T79	0	631	0	0
T80	0	382	0	0
T104	0	7	0	0
T105	0	7	0	0
T106	0	89	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11090	0	0
T6	4259	49	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	133	0	0
T73	0	56	0	0
T74	0	674	0	0
T76	0	203	0	0
T79	0	618	0	0
T80	0	366	0	0
T104	0	9	0	0
T105	0	28	0	0
T106	0	92	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11107	0	0
T6	4259	44	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	178	0	0
T73	0	86	0	0
T74	0	649	0	0
T76	0	171	0	0
T79	0	634	0	0
T80	0	337	0	0
T104	0	8	0	0
T105	0	31	0	0
T106	0	72	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11210	0	0
T6	4259	40	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	165	0	0
T73	0	66	0	0
T74	0	651	0	0
T76	0	209	0	0
T79	0	694	0	0
T80	0	341	0	0
T104	0	16	0	0
T105	0	21	0	0
T106	0	82	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11093	0	0
T6	4259	49	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	190	0	0
T73	0	85	0	0
T74	0	617	0	0
T76	0	191	0	0
T79	0	634	0	0
T80	0	335	0	0
T104	0	20	0	0
T105	0	22	0	0
T106	0	62	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11226	0	0
T6	4259	36	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	181	0	0
T73	0	97	0	0
T74	0	684	0	0
T76	0	223	0	0
T79	0	630	0	0
T80	0	334	0	0
T104	0	18	0	0
T105	0	15	0	0
T106	0	80	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	11471	0	0
T6	4259	55	0	0
T7	6087	0	0	0
T8	2174	0	0	0
T9	156227	0	0	0
T10	3850	0	0	0
T11	3049	0	0	0
T12	4066	0	0	0
T13	3073	0	0	0
T14	2226	0	0	0
T22	21786	0	0	0
T48	0	214	0	0
T73	0	78	0	0
T74	0	659	0	0
T76	0	222	0	0
T79	0	616	0	0
T80	0	391	0	0
T104	0	15	0	0
T105	0	13	0	0
T106	0	65	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5416	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	19	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	100	0	0
T74	0	372	0	0
T76	0	137	0	0
T79	0	261	0	0
T80	0	98	0	0
T84	0	19	0	0
T106	0	16	0	0
T107	0	17	0	0
T108	0	6	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5379	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	22	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	81	0	0
T74	0	432	0	0
T76	0	106	0	0
T79	0	262	0	0
T80	0	104	0	0
T84	0	20	0	0
T106	0	19	0	0
T107	0	35	0	0
T108	0	14	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5287	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	20	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	83	0	0
T74	0	391	0	0
T76	0	129	0	0
T79	0	248	0	0
T80	0	118	0	0
T84	0	36	0	0
T106	0	33	0	0
T107	0	46	0	0
T108	0	3	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5466	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	35	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	100	0	0
T74	0	426	0	0
T76	0	118	0	0
T79	0	289	0	0
T80	0	71	0	0
T84	0	53	0	0
T106	0	28	0	0
T107	0	31	0	0
T108	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5181	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	39	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	57	0	0
T74	0	405	0	0
T76	0	101	0	0
T79	0	229	0	0
T80	0	94	0	0
T84	0	18	0	0
T106	0	19	0	0
T107	0	37	0	0
T108	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5315	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	36	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	94	0	0
T74	0	376	0	0
T76	0	113	0	0
T79	0	241	0	0
T80	0	89	0	0
T84	0	22	0	0
T106	0	17	0	0
T107	0	19	0	0
T108	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5416	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	23	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	71	0	0
T74	0	419	0	0
T76	0	97	0	0
T79	0	233	0	0
T80	0	75	0	0
T84	0	26	0	0
T106	0	4	0	0
T107	0	32	0	0
T108	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13496882	5510	0	0
T15	2528	0	0	0
T24	42570	0	0	0
T37	70299	0	0	0
T38	1343	0	0	0
T39	26196	0	0	0
T43	2450	0	0	0
T44	3698	0	0	0
T48	11741	25	0	0
T60	1926	0	0	0
T64	13430	0	0	0
T73	0	75	0	0
T74	0	403	0	0
T76	0	119	0	0
T79	0	251	0	0
T80	0	95	0	0
T84	0	24	0	0
T106	0	24	0	0
T107	0	20	0	0
T108	0	4	0	0