Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	590686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

353012

1

T1

134

T2

410

T6

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	502598	1			T1	186		T2	587		T4	1
values[0x0]	220468	1			T1	104		T2	258		T6	50
values[0x1]	220632	1			T1	89		T2	283		T6	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	495442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

448256

1

T1

164

T2

510

T6

96

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3047	1			T2	4		T7	1		T9	33
valid_sources[0x01]	3079	1			T2	11		T9	32		T20	1
valid_sources[0x02]	3250	1			T2	9		T7	4		T9	43
valid_sources[0x03]	3799	1			T7	2		T8	3		T9	28
valid_sources[0x04]	3849	1			T2	7		T6	1		T7	5
valid_sources[0x05]	3900	1			T6	2		T7	2		T9	28
valid_sources[0x06]	4171	1			T2	13		T6	2		T8	3
valid_sources[0x07]	3416	1			T2	8		T9	39		T11	1
valid_sources[0x08]	3144	1			T6	1		T7	2		T9	30
valid_sources[0x09]	4244	1			T7	2		T8	5		T9	31
valid_sources[0x0a]	3296	1			T2	4		T6	1		T7	3
valid_sources[0x0b]	3045	1			T2	1		T6	3		T7	4
valid_sources[0x0c]	3568	1			T2	3		T6	1		T9	34
valid_sources[0x0d]	3171	1			T2	4		T7	1		T9	29
valid_sources[0x0e]	4626	1			T2	3		T6	2		T7	4
valid_sources[0x0f]	3546	1			T2	6		T6	1		T7	3
valid_sources[0x10]	4105	1			T2	7		T6	2		T7	1
valid_sources[0x11]	6376	1			T7	2		T9	39		T11	4
valid_sources[0x12]	3347	1			T2	4		T7	2		T9	40
valid_sources[0x13]	3517	1			T2	18		T7	1		T9	34
valid_sources[0x14]	3813	1			T2	2		T6	1		T7	2
valid_sources[0x15]	3446	1			T2	12		T9	40		T11	1
valid_sources[0x16]	4201	1			T6	2		T9	46		T11	4
valid_sources[0x17]	3817	1			T2	12		T6	1		T8	2
valid_sources[0x18]	3525	1			T2	3		T7	1		T9	38
valid_sources[0x19]	3407	1			T2	11		T6	2		T7	2
valid_sources[0x1a]	3641	1			T2	2		T6	1		T9	40
valid_sources[0x1b]	3044	1			T8	1		T9	37		T11	4
valid_sources[0x1c]	3605	1			T2	1		T6	1		T7	2
valid_sources[0x1d]	3216	1			T2	5		T7	3		T9	43
valid_sources[0x1e]	3099	1			T2	7		T6	1		T7	1
valid_sources[0x1f]	3652	1			T2	2		T6	1		T7	2
valid_sources[0x20]	3487	1			T2	3		T7	1		T9	25
valid_sources[0x21]	3378	1			T2	7		T5	1		T7	1
valid_sources[0x22]	3005	1			T2	2		T9	31		T20	2
valid_sources[0x23]	3471	1			T2	12		T6	2		T7	4
valid_sources[0x24]	3855	1			T2	5		T6	4		T7	1
valid_sources[0x25]	3315	1			T7	1		T9	19		T11	2
valid_sources[0x26]	3517	1			T2	4		T9	31		T11	4
valid_sources[0x27]	3302	1			T2	3		T7	3		T9	34
valid_sources[0x28]	4125	1			T6	3		T9	39		T11	4
valid_sources[0x29]	3165	1			T2	2		T6	1		T7	1
valid_sources[0x2a]	3464	1			T2	4		T6	1		T7	1
valid_sources[0x2b]	3223	1			T2	7		T6	2		T7	2
valid_sources[0x2c]	3082	1			T9	27		T21	5		T22	5
valid_sources[0x2d]	3219	1			T2	8		T7	1		T9	33
valid_sources[0x2e]	6568	1			T2	8		T8	1		T9	22
valid_sources[0x2f]	4042	1			T2	8		T6	1		T7	1
valid_sources[0x30]	3628	1			T2	17		T6	2		T7	4
valid_sources[0x31]	3300	1			T2	3		T6	1		T9	42
valid_sources[0x32]	3579	1			T7	4		T8	1		T9	38
valid_sources[0x33]	3448	1			T2	4		T7	1		T9	32
valid_sources[0x34]	3230	1			T2	3		T7	2		T9	37
valid_sources[0x35]	3090	1			T6	1		T7	2		T9	36
valid_sources[0x36]	3153	1			T2	8		T6	1		T7	1
valid_sources[0x37]	3037	1			T6	1		T9	38		T11	3
valid_sources[0x38]	3874	1			T2	3		T6	1		T7	1
valid_sources[0x39]	4192	1			T6	1		T7	2		T9	37
valid_sources[0x3a]	6677	1			T2	1		T6	1		T7	4
valid_sources[0x3b]	3336	1			T2	4		T7	1		T8	1
valid_sources[0x3c]	3751	1			T2	15		T6	1		T7	2
valid_sources[0x3d]	4267	1			T7	1		T9	37		T21	6
valid_sources[0x3e]	3432	1			T2	9		T7	3		T9	33
valid_sources[0x3f]	3186	1			T2	6		T6	1		T9	36
valid_sources[0x40]	3738	1			T2	4		T6	1		T7	1
valid_sources[0x41]	3176	1			T7	2		T9	24		T11	1
valid_sources[0x42]	5343	1			T7	1		T9	31		T11	4
valid_sources[0x43]	3769	1			T6	1		T9	27		T21	17
valid_sources[0x44]	7112	1			T2	14		T9	26		T11	1
valid_sources[0x45]	3621	1			T2	9		T6	1		T7	1
valid_sources[0x46]	3081	1			T2	1		T9	33		T21	6
valid_sources[0x47]	3731	1			T2	6		T6	1		T7	4
valid_sources[0x48]	3531	1			T6	2		T9	30		T11	2
valid_sources[0x49]	3182	1			T2	1		T6	1		T7	1
valid_sources[0x4a]	3248	1			T2	10		T6	2		T7	1
valid_sources[0x4b]	3263	1			T7	1		T9	34		T11	1
valid_sources[0x4c]	3517	1			T2	3		T7	2		T9	37
valid_sources[0x4d]	3151	1			T2	3		T6	3		T7	2
valid_sources[0x4e]	3565	1			T1	379		T7	1		T9	33
valid_sources[0x4f]	3175	1			T2	2		T6	1		T7	2
valid_sources[0x50]	3147	1			T7	3		T8	1		T9	34
valid_sources[0x51]	3092	1			T2	7		T8	2		T9	35
valid_sources[0x52]	3634	1			T2	14		T6	1		T7	3
valid_sources[0x53]	3291	1			T7	1		T9	40		T21	4
valid_sources[0x54]	3714	1			T2	9		T6	1		T7	4
valid_sources[0x55]	3261	1			T7	4		T9	26		T11	1
valid_sources[0x56]	4474	1			T7	2		T9	30		T11	1
valid_sources[0x57]	3796	1			T2	4		T6	1		T8	4
valid_sources[0x58]	3736	1			T2	10		T7	4		T9	28
valid_sources[0x59]	3819	1			T2	1		T7	1		T9	29
valid_sources[0x5a]	3185	1			T6	2		T7	1		T8	2
valid_sources[0x5b]	3123	1			T6	1		T7	1		T9	36
valid_sources[0x5c]	3532	1			T7	1		T9	35		T11	2
valid_sources[0x5d]	3374	1			T9	40		T11	1		T21	6
valid_sources[0x5e]	3634	1			T6	2		T7	2		T9	44
valid_sources[0x5f]	6686	1			T2	4		T6	1		T7	1
valid_sources[0x60]	4083	1			T2	3		T7	1		T9	32
valid_sources[0x61]	3569	1			T2	5		T6	2		T7	2
valid_sources[0x62]	3218	1			T2	7		T7	3		T8	9
valid_sources[0x63]	3420	1			T7	1		T9	27		T11	2
valid_sources[0x64]	3380	1			T2	10		T6	2		T7	3
valid_sources[0x65]	3774	1			T2	7		T9	30		T11	3
valid_sources[0x66]	3337	1			T6	1		T7	1		T9	36
valid_sources[0x67]	3409	1			T7	1		T9	35		T20	1
valid_sources[0x68]	3201	1			T6	2		T7	4		T9	37
valid_sources[0x69]	3312	1			T9	20		T11	1		T21	8
valid_sources[0x6a]	3570	1			T2	6		T7	4		T8	4
valid_sources[0x6b]	3407	1			T2	2		T9	32		T11	3
valid_sources[0x6c]	3170	1			T2	10		T6	1		T7	2
valid_sources[0x6d]	3196	1			T2	5		T6	1		T9	35
valid_sources[0x6e]	3722	1			T6	2		T9	38		T11	1
valid_sources[0x6f]	3707	1			T2	4		T6	1		T7	3
valid_sources[0x70]	3347	1			T7	1		T8	9		T9	25
valid_sources[0x71]	4311	1			T7	2		T8	3		T9	36
valid_sources[0x72]	3015	1			T9	41		T11	4		T20	1
valid_sources[0x73]	3352	1			T2	2		T6	1		T7	2
valid_sources[0x74]	3794	1			T6	2		T9	23		T11	1
valid_sources[0x75]	2951	1			T7	1		T9	29		T11	1
valid_sources[0x76]	2939	1			T2	11		T7	4		T8	2
valid_sources[0x77]	3459	1			T7	1		T9	32		T11	2
valid_sources[0x78]	3154	1			T6	2		T9	40		T20	1
valid_sources[0x79]	3280	1			T6	2		T9	29		T11	3
valid_sources[0x7a]	3592	1			T2	8		T6	1		T7	1
valid_sources[0x7b]	3332	1			T2	13		T7	2		T9	27
valid_sources[0x7c]	3322	1			T9	45		T20	1		T21	5
valid_sources[0x7d]	3381	1			T2	9		T6	2		T9	25
valid_sources[0x7e]	3158	1			T2	1		T6	3		T7	2
valid_sources[0x7f]	3509	1			T2	5		T7	3		T9	35
valid_sources[0x80]	3426	1			T2	12		T7	1		T8	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

235065

1

T1

85

T2

275

T6

49

values[0x0]

all_enables

biggest_size

76927

1

T1

26

T2

89

T6

16

values[0x1]

all_enables

biggest_size

41020

1

T1

23

T2

46

T6

9