Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T8
1	0	Covered	T7,T9,T21

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	49308971	7821	0	0
CascadeEffAonToRstPorAboveRise_A	49308971	7821	0	0
CascadeEffAonToRstPorIoAboveFall_A	47334817	7821	0	0
CascadeEffAonToRstPorIoAboveRise_A	47334817	7821	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	23668029	7821	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	23668029	7821	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	11833716	7821	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	11833716	7821	0	0
CascadeEffAonToRstPorUcbAboveFall_A	23668062	7821	0	0
CascadeEffAonToRstPorUcbAboveRise_A	23668062	7821	0	0
CascadeLcToLcAboveFall_A	49308971	20533	0	0
CascadeLcToLcAboveRise_A	49308971	20533	0	0
CascadeLcToLcAonAboveFall_A	1494460	20533	0	0
CascadeLcToLcAonAboveRise_A	1494460	20533	0	0
CascadeLcToLcShadowedAboveFall_A	49308971	20533	0	0
CascadeLcToLcShadowedAboveRise_A	49308971	20533	0	0
CascadePorToAonAboveFall_A	1494460	6196	0	0
CascadeSysToSysAboveFall_A	49308971	20533	0	0
CascadeSysToSysAboveRise_A	49308971	20533	0	0
ScanRstToAonRise_A	1494460	201	0	0
StablePorToAonRise_A	1494460	7821	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10459907	20533	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10459907	20533	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10459907	20533	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10459907	20533	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	11833716	20533	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	11833716	20533	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10459907	20533	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10459907	20533	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10459907	20533	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10459907	20533	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	7821	0	0
T1	11672	2	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	2	0	0
T7	18921	2	0	0
T8	9801	2	0	0
T9	261204	56	0	0
T10	121637	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	7821	0	0
T1	11672	2	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	2	0	0
T7	18921	2	0	0
T8	9801	2	0	0
T9	261204	56	0	0
T10	121637	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47334817	7821	0	0
T1	11212	2	0	0
T2	47626	1	0	0
T3	23334	8	0	0
T4	15877	2	0	0
T5	19043	2	0	0
T6	16782	2	0	0
T7	18170	2	0	0
T8	9408	2	0	0
T9	250765	56	0	0
T10	116767	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47334817	7821	0	0
T1	11212	2	0	0
T2	47626	1	0	0
T3	23334	8	0	0
T4	15877	2	0	0
T5	19043	2	0	0
T6	16782	2	0	0
T7	18170	2	0	0
T8	9408	2	0	0
T9	250765	56	0	0
T10	116767	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668029	7821	0	0
T1	5605	2	0	0
T2	23814	1	0	0
T3	11660	8	0	0
T4	7938	2	0	0
T5	9520	2	0	0
T6	8391	2	0	0
T7	9085	2	0	0
T8	4702	2	0	0
T9	125374	56	0	0
T10	58386	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668029	7821	0	0
T1	5605	2	0	0
T2	23814	1	0	0
T3	11660	8	0	0
T4	7938	2	0	0
T5	9520	2	0	0
T6	8391	2	0	0
T7	9085	2	0	0
T8	4702	2	0	0
T9	125374	56	0	0
T10	58386	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	7821	0	0
T1	2800	2	0	0
T2	11906	1	0	0
T3	5827	8	0	0
T4	3969	2	0	0
T5	4759	2	0	0
T6	4194	2	0	0
T7	4540	2	0	0
T8	2350	2	0	0
T9	62686	56	0	0
T10	29190	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	7821	0	0
T1	2800	2	0	0
T2	11906	1	0	0
T3	5827	8	0	0
T4	3969	2	0	0
T5	4759	2	0	0
T6	4194	2	0	0
T7	4540	2	0	0
T8	2350	2	0	0
T9	62686	56	0	0
T10	29190	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668062	7821	0	0
T1	5604	2	0	0
T2	23814	1	0	0
T3	11657	8	0	0
T4	7937	2	0	0
T5	9521	2	0	0
T6	8390	2	0	0
T7	9083	2	0	0
T8	4702	2	0	0
T9	125369	56	0	0
T10	58373	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668062	7821	0	0
T1	5604	2	0	0
T2	23814	1	0	0
T3	11657	8	0	0
T4	7937	2	0	0
T5	9521	2	0	0
T6	8390	2	0	0
T7	9083	2	0	0
T8	4702	2	0	0
T9	125369	56	0	0
T10	58373	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	20533	0	0
T1	11672	6	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	6	0	0
T7	18921	6	0	0
T8	9801	6	0	0
T9	261204	153	0	0
T10	121637	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	20533	0	0
T1	11672	6	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	6	0	0
T7	18921	6	0	0
T8	9801	6	0	0
T9	261204	153	0	0
T10	121637	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	20533	0	0
T1	349	6	0	0
T2	1487	1	0	0
T3	730	8	0	0
T4	495	2	0	0
T5	593	2	0	0
T6	523	6	0	0
T7	566	6	0	0
T8	293	6	0	0
T9	8016	153	0	0
T10	3664	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	20533	0	0
T1	349	6	0	0
T2	1487	1	0	0
T3	730	8	0	0
T4	495	2	0	0
T5	593	2	0	0
T6	523	6	0	0
T7	566	6	0	0
T8	293	6	0	0
T9	8016	153	0	0
T10	3664	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	20533	0	0
T1	11672	6	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	6	0	0
T7	18921	6	0	0
T8	9801	6	0	0
T9	261204	153	0	0
T10	121637	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	20533	0	0
T1	11672	6	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	6	0	0
T7	18921	6	0	0
T8	9801	6	0	0
T9	261204	153	0	0
T10	121637	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	6196	0	0
T1	349	1	0	0
T2	1487	1	0	0
T3	730	8	0	0
T4	495	14	0	0
T5	593	17	0	0
T6	523	1	0	0
T7	566	1	0	0
T8	293	1	0	0
T9	8016	23	0	0
T10	3664	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	20533	0	0
T1	11672	6	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	6	0	0
T7	18921	6	0	0
T8	9801	6	0	0
T9	261204	153	0	0
T10	121637	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49308971	20533	0	0
T1	11672	6	0	0
T2	49612	1	0	0
T3	24299	8	0	0
T4	16539	2	0	0
T5	19839	2	0	0
T6	17479	6	0	0
T7	18921	6	0	0
T8	9801	6	0	0
T9	261204	153	0	0
T10	121637	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	201	0	0
T8	293	1	0	0
T9	8016	6	0	0
T10	3664	0	0	0
T11	419	0	0	0
T12	590	0	0	0
T13	399	0	0	0
T20	446	0	0	0
T21	2148	3	0	0
T22	540	0	0	0
T45	4045	2	0	0
T46	0	3	0	0
T50	0	1	0	0
T83	0	1	0	0
T87	0	7	0	0
T100	0	2	0	0
T101	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	7821	0	0
T1	349	2	0	0
T2	1487	1	0	0
T3	730	8	0	0
T4	495	2	0	0
T5	593	2	0	0
T6	523	2	0	0
T7	566	2	0	0
T8	293	2	0	0
T9	8016	56	0	0
T10	3664	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	20533	0	0
T1	2800	6	0	0
T2	11906	1	0	0
T3	5827	8	0	0
T4	3969	2	0	0
T5	4759	2	0	0
T6	4194	6	0	0
T7	4540	6	0	0
T8	2350	6	0	0
T9	62686	153	0	0
T10	29190	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	20533	0	0
T1	2800	6	0	0
T2	11906	1	0	0
T3	5827	8	0	0
T4	3969	2	0	0
T5	4759	2	0	0
T6	4194	6	0	0
T7	4540	6	0	0
T8	2350	6	0	0
T9	62686	153	0	0
T10	29190	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10459907	20533	0	0
T1	2467	6	0	0
T2	11863	1	0	0
T3	5284	8	0	0
T4	3854	2	0	0
T5	4574	2	0	0
T6	3954	6	0	0
T7	4394	6	0	0
T8	2111	6	0	0
T9	49150	153	0	0
T10	26381	102	0	0