Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T46
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T46
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T46
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11833716	13521	0	0
gen_assertions[0].RstEnOn_A	11833716	1001	0	0
gen_assertions[0].RstNOff_A	11833716	13521	0	0
gen_assertions[0].RstNOn_A	11833716	1001	0	0
gen_assertions[1].RstEnOff_A	47334817	12353	0	0
gen_assertions[1].RstEnOn_A	47334817	974	0	0
gen_assertions[1].RstNOff_A	47334817	12353	0	0
gen_assertions[1].RstNOn_A	47334817	974	0	0
gen_assertions[2].RstEnOff_A	23668029	12380	0	0
gen_assertions[2].RstEnOn_A	23668029	949	0	0
gen_assertions[2].RstNOff_A	23668029	12380	0	0
gen_assertions[2].RstNOn_A	23668029	949	0	0
gen_assertions[3].RstEnOff_A	23668062	12417	0	0
gen_assertions[3].RstEnOn_A	23668062	979	0	0
gen_assertions[3].RstNOff_A	23668062	12417	0	0
gen_assertions[3].RstNOn_A	23668062	979	0	0
gen_assertions[4].RstEnOff_A	1494460	20269	0	0
gen_assertions[4].RstEnOn_A	1494460	1047	0	0
gen_assertions[4].RstNOff_A	1494460	20269	0	0
gen_assertions[4].RstNOn_A	1494460	1047	0	0
gen_assertions[5].RstEnOff_A	11833716	13765	0	0
gen_assertions[5].RstEnOn_A	11833716	1086	0	0
gen_assertions[5].RstNOff_A	11833716	13765	0	0
gen_assertions[5].RstNOn_A	11833716	1086	0	0
gen_assertions[6].RstEnOff_A	11833716	13797	0	0
gen_assertions[6].RstEnOn_A	11833716	1122	0	0
gen_assertions[6].RstNOff_A	11833716	13797	0	0
gen_assertions[6].RstNOn_A	11833716	1122	0	0
gen_assertions[7].RstEnOff_A	11833716	13896	0	0
gen_assertions[7].RstEnOn_A	11833716	1223	0	0
gen_assertions[7].RstNOff_A	11833716	13896	0	0
gen_assertions[7].RstNOn_A	11833716	1223	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13521	0	0
T1	2800	4	0	0
T2	11906	5	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	4	0	0
T8	2350	4	0	0
T9	62686	109	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1001	0	0
T2	11906	5	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	0	0	0
T8	2350	0	0	0
T9	62686	14	0	0
T10	29190	0	0	0
T11	3354	7	0	0
T22	0	1	0	0
T33	0	6	0	0
T46	0	20	0	0
T56	0	8	0	0
T63	0	1	0	0
T83	0	1	0	0
T84	0	7	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13521	0	0
T1	2800	4	0	0
T2	11906	5	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	4	0	0
T8	2350	4	0	0
T9	62686	109	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1001	0	0
T2	11906	5	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	0	0	0
T8	2350	0	0	0
T9	62686	14	0	0
T10	29190	0	0	0
T11	3354	7	0	0
T22	0	1	0	0
T33	0	6	0	0
T46	0	20	0	0
T56	0	8	0	0
T63	0	1	0	0
T83	0	1	0	0
T84	0	7	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47334817	12353	0	0
T1	11212	4	0	0
T2	47626	10	0	0
T3	23334	0	0	0
T4	15877	0	0	0
T5	19043	0	0	0
T6	16782	4	0	0
T7	18170	3	0	0
T8	9408	4	0	0
T9	250765	106	0	0
T10	116767	67	0	0
T11	0	15	0	0
T20	0	3	0	0
T21	0	29	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47334817	974	0	0
T2	47626	10	0	0
T3	23334	0	0	0
T4	15877	0	0	0
T5	19043	0	0	0
T6	16782	0	0	0
T7	18170	0	0	0
T8	9408	0	0	0
T9	250765	14	0	0
T10	116767	0	0	0
T11	13420	3	0	0
T33	0	5	0	0
T46	0	19	0	0
T56	0	9	0	0
T57	0	2	0	0
T84	0	9	0	0
T85	0	5	0	0
T86	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47334817	12353	0	0
T1	11212	4	0	0
T2	47626	10	0	0
T3	23334	0	0	0
T4	15877	0	0	0
T5	19043	0	0	0
T6	16782	4	0	0
T7	18170	3	0	0
T8	9408	4	0	0
T9	250765	106	0	0
T10	116767	67	0	0
T11	0	15	0	0
T20	0	3	0	0
T21	0	29	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47334817	974	0	0
T2	47626	10	0	0
T3	23334	0	0	0
T4	15877	0	0	0
T5	19043	0	0	0
T6	16782	0	0	0
T7	18170	0	0	0
T8	9408	0	0	0
T9	250765	14	0	0
T10	116767	0	0	0
T11	13420	3	0	0
T33	0	5	0	0
T46	0	19	0	0
T56	0	9	0	0
T57	0	2	0	0
T84	0	9	0	0
T85	0	5	0	0
T86	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668029	12380	0	0
T1	5605	4	0	0
T2	23814	10	0	0
T3	11660	0	0	0
T4	7938	0	0	0
T5	9520	0	0	0
T6	8391	4	0	0
T7	9085	3	0	0
T8	4702	4	0	0
T9	125374	105	0	0
T10	58386	67	0	0
T11	0	15	0	0
T20	0	3	0	0
T21	0	29	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668029	949	0	0
T2	23814	10	0	0
T3	11660	0	0	0
T4	7938	0	0	0
T5	9520	0	0	0
T6	8391	0	0	0
T7	9085	0	0	0
T8	4702	0	0	0
T9	125374	13	0	0
T10	58386	0	0	0
T11	6710	0	0	0
T33	0	3	0	0
T46	0	16	0	0
T56	0	9	0	0
T57	0	4	0	0
T62	0	1	0	0
T84	0	10	0	0
T85	0	6	0	0
T86	0	2	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668029	12380	0	0
T1	5605	4	0	0
T2	23814	10	0	0
T3	11660	0	0	0
T4	7938	0	0	0
T5	9520	0	0	0
T6	8391	4	0	0
T7	9085	3	0	0
T8	4702	4	0	0
T9	125374	105	0	0
T10	58386	67	0	0
T11	0	15	0	0
T20	0	3	0	0
T21	0	29	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668029	949	0	0
T2	23814	10	0	0
T3	11660	0	0	0
T4	7938	0	0	0
T5	9520	0	0	0
T6	8391	0	0	0
T7	9085	0	0	0
T8	4702	0	0	0
T9	125374	13	0	0
T10	58386	0	0	0
T11	6710	0	0	0
T33	0	3	0	0
T46	0	16	0	0
T56	0	9	0	0
T57	0	4	0	0
T62	0	1	0	0
T84	0	10	0	0
T85	0	6	0	0
T86	0	2	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668062	12417	0	0
T1	5604	4	0	0
T2	23814	13	0	0
T3	11657	0	0	0
T4	7937	0	0	0
T5	9521	0	0	0
T6	8390	4	0	0
T7	9083	3	0	0
T8	4702	4	0	0
T9	125369	103	0	0
T10	58373	67	0	0
T11	0	15	0	0
T20	0	3	0	0
T21	0	29	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668062	979	0	0
T2	23814	13	0	0
T3	11657	0	0	0
T4	7937	0	0	0
T5	9521	0	0	0
T6	8390	0	0	0
T7	9083	0	0	0
T8	4702	0	0	0
T9	125369	12	0	0
T10	58373	0	0	0
T11	6709	0	0	0
T33	0	5	0	0
T46	0	16	0	0
T56	0	8	0	0
T57	0	4	0	0
T84	0	9	0	0
T85	0	8	0	0
T86	0	1	0	0
T87	0	17	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668062	12417	0	0
T1	5604	4	0	0
T2	23814	13	0	0
T3	11657	0	0	0
T4	7937	0	0	0
T5	9521	0	0	0
T6	8390	4	0	0
T7	9083	3	0	0
T8	4702	4	0	0
T9	125369	103	0	0
T10	58373	67	0	0
T11	0	15	0	0
T20	0	3	0	0
T21	0	29	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23668062	979	0	0
T2	23814	13	0	0
T3	11657	0	0	0
T4	7937	0	0	0
T5	9521	0	0	0
T6	8390	0	0	0
T7	9083	0	0	0
T8	4702	0	0	0
T9	125369	12	0	0
T10	58373	0	0	0
T11	6709	0	0	0
T33	0	5	0	0
T46	0	16	0	0
T56	0	8	0	0
T57	0	4	0	0
T84	0	9	0	0
T85	0	8	0	0
T86	0	1	0	0
T87	0	17	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	20269	0	0
T1	349	7	0	0
T2	1487	13	0	0
T3	730	3	0	0
T4	495	2	0	0
T5	593	2	0	0
T6	523	6	0	0
T7	566	6	0	0
T8	293	6	0	0
T9	8016	163	0	0
T10	3664	77	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	1047	0	0
T1	349	1	0	0
T2	1487	12	0	0
T3	730	0	0	0
T4	495	0	0	0
T5	593	0	0	0
T6	523	0	0	0
T7	566	0	0	0
T8	293	0	0	0
T9	8016	15	0	0
T10	3664	0	0	0
T33	0	4	0	0
T46	0	19	0	0
T48	0	1	0	0
T56	0	10	0	0
T57	0	5	0	0
T63	0	1	0	0
T84	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	20269	0	0
T1	349	7	0	0
T2	1487	13	0	0
T3	730	3	0	0
T4	495	2	0	0
T5	593	2	0	0
T6	523	6	0	0
T7	566	6	0	0
T8	293	6	0	0
T9	8016	163	0	0
T10	3664	77	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494460	1047	0	0
T1	349	1	0	0
T2	1487	12	0	0
T3	730	0	0	0
T4	495	0	0	0
T5	593	0	0	0
T6	523	0	0	0
T7	566	0	0	0
T8	293	0	0	0
T9	8016	15	0	0
T10	3664	0	0	0
T33	0	4	0	0
T46	0	19	0	0
T48	0	1	0	0
T56	0	10	0	0
T57	0	5	0	0
T63	0	1	0	0
T84	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13765	0	0
T1	2800	4	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	4	0	0
T8	2350	4	0	0
T9	62686	109	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1086	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	0	0	0
T8	2350	0	0	0
T9	62686	12	0	0
T10	29190	0	0	0
T11	3354	0	0	0
T33	0	5	0	0
T35	0	1	0	0
T46	0	19	0	0
T56	0	13	0	0
T57	0	6	0	0
T83	0	1	0	0
T84	0	11	0	0
T85	0	10	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13765	0	0
T1	2800	4	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	4	0	0
T8	2350	4	0	0
T9	62686	109	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1086	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	0	0	0
T8	2350	0	0	0
T9	62686	12	0	0
T10	29190	0	0	0
T11	3354	0	0	0
T33	0	5	0	0
T35	0	1	0	0
T46	0	19	0	0
T56	0	13	0	0
T57	0	6	0	0
T83	0	1	0	0
T84	0	11	0	0
T85	0	10	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13797	0	0
T1	2800	5	0	0
T2	11906	13	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	4	0	0
T8	2350	4	0	0
T9	62686	110	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1122	0	0
T1	2800	1	0	0
T2	11906	13	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	0	0	0
T8	2350	0	0	0
T9	62686	15	0	0
T10	29190	0	0	0
T33	0	5	0	0
T46	0	22	0	0
T48	0	1	0	0
T56	0	14	0	0
T57	0	6	0	0
T62	0	1	0	0
T84	0	12	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13797	0	0
T1	2800	5	0	0
T2	11906	13	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	4	0	0
T8	2350	4	0	0
T9	62686	110	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1122	0	0
T1	2800	1	0	0
T2	11906	13	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	0	0	0
T8	2350	0	0	0
T9	62686	15	0	0
T10	29190	0	0	0
T33	0	5	0	0
T46	0	22	0	0
T48	0	1	0	0
T56	0	14	0	0
T57	0	6	0	0
T62	0	1	0	0
T84	0	12	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13896	0	0
T1	2800	4	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	5	0	0
T8	2350	4	0	0
T9	62686	111	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1223	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	1	0	0
T8	2350	0	0	0
T9	62686	16	0	0
T10	29190	0	0	0
T11	3354	0	0	0
T33	0	3	0	0
T46	0	15	0	0
T56	0	12	0	0
T57	0	8	0	0
T62	0	1	0	0
T63	0	1	0	0
T83	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	13896	0	0
T1	2800	4	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	4	0	0
T7	4540	5	0	0
T8	2350	4	0	0
T9	62686	111	0	0
T10	29190	75	0	0
T11	0	16	0	0
T20	0	4	0	0
T21	0	30	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11833716	1223	0	0
T2	11906	12	0	0
T3	5827	0	0	0
T4	3969	0	0	0
T5	4759	0	0	0
T6	4194	0	0	0
T7	4540	1	0	0
T8	2350	0	0	0
T9	62686	16	0	0
T10	29190	0	0	0
T11	3354	0	0	0
T33	0	3	0	0
T46	0	15	0	0
T56	0	12	0	0
T57	0	8	0	0
T62	0	1	0	0
T63	0	1	0	0
T83	0	1	0	0