Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11152592	6832	0	0
alert_regwen_rd_A	11152592	3889	0	0
cpu_regwen_rd_A	11152592	3820	0	0
sw_rst_ctrl_n_0_rd_A	11152592	8543	0	0
sw_rst_ctrl_n_1_rd_A	11152592	8596	0	0
sw_rst_ctrl_n_2_rd_A	11152592	8383	0	0
sw_rst_ctrl_n_3_rd_A	11152592	8667	0	0
sw_rst_ctrl_n_4_rd_A	11152592	8637	0	0
sw_rst_ctrl_n_5_rd_A	11152592	8503	0	0
sw_rst_ctrl_n_6_rd_A	11152592	8437	0	0
sw_rst_ctrl_n_7_rd_A	11152592	8431	0	0
sw_rst_regwen_0_rd_A	11152592	4463	0	0
sw_rst_regwen_1_rd_A	11152592	4476	0	0
sw_rst_regwen_2_rd_A	11152592	4423	0	0
sw_rst_regwen_3_rd_A	11152592	4492	0	0
sw_rst_regwen_4_rd_A	11152592	4303	0	0
sw_rst_regwen_5_rd_A	11152592	4600	0	0
sw_rst_regwen_6_rd_A	11152592	4512	0	0
sw_rst_regwen_7_rd_A	11152592	4607	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	6832	0	0
T64	4220	62	0	0
T65	4551	15	0	0
T66	5479	230	0	0
T67	7697	224	0	0
T90	3007	93	0	0
T91	4402	134	0	0
T92	21082	1	0	0
T94	2445	15	0	0
T96	3361	500	0	0
T97	9804	398	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	3889	0	0
T14	3451	0	0	0
T15	3628	0	0	0
T16	1981	0	0	0
T36	33968	62	0	0
T37	5288	0	0	0
T38	2136	0	0	0
T39	1521	0	0	0
T40	5679	0	0	0
T62	2493	0	0	0
T63	5182	0	0	0
T86	0	260	0	0
T87	0	762	0	0
T101	0	61	0	0
T102	0	245	0	0
T103	0	121	0	0
T128	0	59	0	0
T129	0	36	0	0
T130	0	218	0	0
T131	0	27	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	3820	0	0
T14	3451	0	0	0
T15	3628	0	0	0
T16	1981	0	0	0
T36	33968	38	0	0
T37	5288	0	0	0
T38	2136	0	0	0
T39	1521	0	0	0
T40	5679	0	0	0
T62	2493	0	0	0
T63	5182	0	0	0
T86	0	251	0	0
T87	0	762	0	0
T101	0	48	0	0
T102	0	211	0	0
T103	0	99	0	0
T128	0	51	0	0
T129	0	43	0	0
T130	0	183	0	0
T131	0	22	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8543	0	0
T2	11863	135	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	41	0	0
T36	0	63	0	0
T63	0	23	0	0
T83	0	9	0	0
T85	0	148	0	0
T86	0	251	0	0
T87	0	1001	0	0
T101	0	43	0	0
T132	0	140	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8596	0	0
T2	11863	113	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	31	0	0
T36	0	38	0	0
T63	0	2	0	0
T83	0	7	0	0
T85	0	148	0	0
T86	0	292	0	0
T87	0	1036	0	0
T101	0	92	0	0
T132	0	165	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8383	0	0
T2	11863	153	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	42	0	0
T36	0	55	0	0
T63	0	3	0	0
T83	0	15	0	0
T85	0	140	0	0
T86	0	249	0	0
T87	0	976	0	0
T101	0	74	0	0
T132	0	92	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8667	0	0
T2	11863	98	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	50	0	0
T36	0	35	0	0
T63	0	5	0	0
T83	0	8	0	0
T85	0	158	0	0
T86	0	272	0	0
T87	0	1064	0	0
T101	0	74	0	0
T132	0	137	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8637	0	0
T2	11863	112	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	31	0	0
T36	0	53	0	0
T63	0	13	0	0
T83	0	13	0	0
T85	0	157	0	0
T86	0	262	0	0
T87	0	1065	0	0
T101	0	58	0	0
T132	0	110	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8503	0	0
T2	11863	96	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	28	0	0
T36	0	32	0	0
T63	0	14	0	0
T83	0	20	0	0
T85	0	131	0	0
T86	0	239	0	0
T87	0	998	0	0
T101	0	58	0	0
T132	0	108	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8437	0	0
T2	11863	117	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	47	0	0
T36	0	45	0	0
T63	0	21	0	0
T83	0	10	0	0
T85	0	160	0	0
T86	0	240	0	0
T87	0	966	0	0
T101	0	79	0	0
T132	0	137	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	8431	0	0
T2	11863	151	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T22	0	40	0	0
T36	0	54	0	0
T63	0	12	0	0
T83	0	11	0	0
T85	0	162	0	0
T86	0	268	0	0
T87	0	1026	0	0
T101	0	51	0	0
T132	0	105	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4463	0	0
T2	11863	22	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	54	0	0
T63	0	2	0	0
T83	0	2	0	0
T85	0	44	0	0
T86	0	233	0	0
T87	0	802	0	0
T101	0	65	0	0
T132	0	18	0	0
T133	0	23	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4476	0	0
T2	11863	11	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	49	0	0
T63	0	4	0	0
T83	0	10	0	0
T85	0	40	0	0
T86	0	279	0	0
T87	0	734	0	0
T101	0	56	0	0
T132	0	17	0	0
T133	0	23	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4423	0	0
T2	11863	27	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	59	0	0
T63	0	2	0	0
T83	0	4	0	0
T85	0	28	0	0
T86	0	206	0	0
T87	0	806	0	0
T101	0	36	0	0
T132	0	5	0	0
T133	0	14	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4492	0	0
T2	11863	12	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	36	0	0
T83	0	5	0	0
T85	0	30	0	0
T86	0	254	0	0
T87	0	804	0	0
T101	0	63	0	0
T132	0	14	0	0
T133	0	26	0	0
T134	0	22	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4303	0	0
T2	11863	28	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	56	0	0
T63	0	3	0	0
T83	0	12	0	0
T85	0	33	0	0
T86	0	210	0	0
T87	0	728	0	0
T101	0	83	0	0
T132	0	19	0	0
T133	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4600	0	0
T2	11863	23	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	45	0	0
T63	0	10	0	0
T83	0	11	0	0
T85	0	33	0	0
T86	0	260	0	0
T87	0	763	0	0
T101	0	36	0	0
T132	0	11	0	0
T133	0	20	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4512	0	0
T2	11863	31	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	52	0	0
T63	0	5	0	0
T83	0	12	0	0
T85	0	40	0	0
T86	0	244	0	0
T87	0	869	0	0
T101	0	62	0	0
T132	0	11	0	0
T133	0	11	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11152592	4607	0	0
T2	11863	20	0	0
T3	5284	0	0	0
T4	3854	0	0	0
T5	4574	0	0	0
T6	3954	0	0	0
T7	4394	0	0	0
T8	2111	0	0	0
T9	49150	0	0	0
T10	26381	0	0	0
T11	2524	0	0	0
T36	0	55	0	0
T63	0	5	0	0
T83	0	2	0	0
T85	0	27	0	0
T86	0	253	0	0
T87	0	820	0	0
T101	0	55	0	0
T132	0	18	0	0
T133	0	16	0	0