Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	665919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

401292

1

T2

2

T4

1097

T5

1141

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	569354	1			T1	1		T4	1500		T5	1729
values[0x0]	248843	1			T2	2		T4	810		T5	710
values[0x1]	249014	1			T2	1		T4	890		T5	630

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	558559	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

508652

1

T2

2

T4

1420

T5

1451

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9083	1			T4	12		T5	70		T9	10
valid_sources[0x01]	3688	1			T4	9		T5	153		T9	6
valid_sources[0x02]	4906	1			T4	15		T9	12		T12	4
valid_sources[0x03]	3701	1			T4	12		T9	9		T12	4
valid_sources[0x04]	3698	1			T4	11		T9	6		T12	3
valid_sources[0x05]	3176	1			T4	12		T9	10		T11	113
valid_sources[0x06]	3779	1			T4	15		T9	9		T11	183
valid_sources[0x07]	3265	1			T4	9		T8	16		T9	7
valid_sources[0x08]	3532	1			T4	8		T9	10		T12	1
valid_sources[0x09]	7589	1			T4	16		T9	9		T11	494
valid_sources[0x0a]	8311	1			T4	14		T8	31		T9	13
valid_sources[0x0b]	3176	1			T1	1		T4	15		T5	113
valid_sources[0x0c]	3184	1			T4	18		T9	8		T12	1
valid_sources[0x0d]	4224	1			T4	18		T8	20		T9	12
valid_sources[0x0e]	3379	1			T4	15		T9	9		T12	1
valid_sources[0x0f]	3106	1			T4	9		T9	8		T13	3
valid_sources[0x10]	3800	1			T4	13		T9	11		T13	3
valid_sources[0x11]	4037	1			T4	12		T8	7		T9	9
valid_sources[0x12]	4533	1			T4	9		T8	122		T9	8
valid_sources[0x13]	3780	1			T4	20		T8	71		T9	7
valid_sources[0x14]	5376	1			T4	6		T9	16		T11	113
valid_sources[0x15]	4106	1			T4	16		T8	7		T9	4
valid_sources[0x16]	3076	1			T4	13		T8	5		T9	9
valid_sources[0x17]	5174	1			T4	13		T9	14		T12	1
valid_sources[0x18]	3541	1			T4	16		T8	50		T9	13
valid_sources[0x19]	3731	1			T4	11		T9	10		T12	1
valid_sources[0x1a]	3121	1			T4	12		T9	3		T13	1
valid_sources[0x1b]	3828	1			T4	17		T9	9		T12	2
valid_sources[0x1c]	4582	1			T4	13		T9	7		T12	1
valid_sources[0x1d]	3220	1			T4	17		T5	252		T9	7
valid_sources[0x1e]	3746	1			T4	6		T9	6		T12	4
valid_sources[0x1f]	4719	1			T4	13		T9	14		T13	2
valid_sources[0x20]	3327	1			T4	14		T9	20		T13	1
valid_sources[0x21]	4169	1			T4	13		T8	4		T9	11
valid_sources[0x22]	3769	1			T4	11		T8	131		T9	10
valid_sources[0x23]	4124	1			T4	9		T9	10		T12	4
valid_sources[0x24]	4543	1			T4	18		T5	58		T9	9
valid_sources[0x25]	4006	1			T4	11		T8	1		T9	16
valid_sources[0x26]	4059	1			T4	15		T5	70		T8	74
valid_sources[0x27]	3402	1			T4	12		T8	59		T9	15
valid_sources[0x28]	3682	1			T4	15		T9	11		T12	1
valid_sources[0x29]	7381	1			T4	9		T9	14		T12	2
valid_sources[0x2a]	3658	1			T4	19		T9	11		T12	2
valid_sources[0x2b]	3300	1			T4	23		T9	10		T12	1
valid_sources[0x2c]	3678	1			T4	8		T8	41		T9	5
valid_sources[0x2d]	4491	1			T4	12		T8	75		T9	10
valid_sources[0x2e]	3432	1			T4	18		T9	5		T12	1
valid_sources[0x2f]	4495	1			T4	15		T9	11		T12	2
valid_sources[0x30]	3473	1			T4	8		T5	156		T9	6
valid_sources[0x31]	4379	1			T4	19		T9	7		T11	370
valid_sources[0x32]	4064	1			T4	8		T8	4		T9	7
valid_sources[0x33]	3385	1			T4	10		T9	17		T12	1
valid_sources[0x34]	3994	1			T4	16		T9	7		T11	649
valid_sources[0x35]	4076	1			T4	9		T9	8		T12	4
valid_sources[0x36]	3504	1			T4	13		T9	15		T12	1
valid_sources[0x37]	3468	1			T4	17		T8	31		T9	11
valid_sources[0x38]	3678	1			T4	6		T9	11		T12	5
valid_sources[0x39]	5256	1			T4	12		T8	6		T9	9
valid_sources[0x3a]	6772	1			T4	21		T9	15		T12	1
valid_sources[0x3b]	4257	1			T4	12		T9	7		T11	242
valid_sources[0x3c]	4666	1			T4	5		T9	17		T12	1
valid_sources[0x3d]	3224	1			T4	12		T8	14		T9	16
valid_sources[0x3e]	4846	1			T4	10		T9	10		T12	5
valid_sources[0x3f]	3476	1			T4	10		T9	7		T12	3
valid_sources[0x40]	7361	1			T4	11		T9	13		T12	5
valid_sources[0x41]	3600	1			T4	11		T5	242		T9	12
valid_sources[0x42]	5145	1			T4	12		T9	9		T11	985
valid_sources[0x43]	4043	1			T4	24		T9	6		T11	366
valid_sources[0x44]	4085	1			T4	11		T5	179		T9	11
valid_sources[0x45]	4132	1			T4	4		T9	13		T11	154
valid_sources[0x46]	3712	1			T4	13		T9	21		T12	2
valid_sources[0x47]	4764	1			T4	13		T8	19		T9	11
valid_sources[0x48]	4351	1			T4	16		T8	47		T9	13
valid_sources[0x49]	3675	1			T4	10		T9	14		T13	1
valid_sources[0x4a]	3731	1			T4	22		T8	13		T9	9
valid_sources[0x4b]	4149	1			T4	14		T8	1		T9	9
valid_sources[0x4c]	4283	1			T4	9		T8	15		T9	13
valid_sources[0x4d]	3690	1			T4	10		T9	5		T12	2
valid_sources[0x4e]	3796	1			T4	5		T8	29		T9	7
valid_sources[0x4f]	5416	1			T4	15		T9	8		T11	112
valid_sources[0x50]	3317	1			T4	6		T9	12		T11	156
valid_sources[0x51]	4011	1			T4	16		T9	7		T11	113
valid_sources[0x52]	3608	1			T4	7		T9	9		T12	3
valid_sources[0x53]	3109	1			T4	11		T9	6		T11	70
valid_sources[0x54]	3767	1			T4	7		T8	9		T9	9
valid_sources[0x55]	4557	1			T4	9		T8	11		T9	9
valid_sources[0x56]	3862	1			T4	7		T8	20		T9	8
valid_sources[0x57]	3510	1			T4	9		T9	10		T12	3
valid_sources[0x58]	3369	1			T4	18		T8	45		T9	8
valid_sources[0x59]	3479	1			T4	8		T9	8		T12	1
valid_sources[0x5a]	3664	1			T4	19		T9	14		T12	1
valid_sources[0x5b]	4446	1			T4	8		T8	71		T9	7
valid_sources[0x5c]	3415	1			T4	17		T8	44		T9	15
valid_sources[0x5d]	4596	1			T4	6		T9	10		T11	113
valid_sources[0x5e]	4506	1			T4	23		T9	10		T13	1
valid_sources[0x5f]	3135	1			T4	14		T9	10		T12	1
valid_sources[0x60]	3352	1			T4	16		T9	8		T12	1
valid_sources[0x61]	3169	1			T4	17		T9	7		T12	1
valid_sources[0x62]	5197	1			T4	16		T9	7		T11	155
valid_sources[0x63]	3538	1			T4	17		T9	10		T24	9
valid_sources[0x64]	4687	1			T4	13		T9	5		T12	2
valid_sources[0x65]	3848	1			T4	5		T9	10		T13	4
valid_sources[0x66]	5269	1			T4	9		T9	8		T11	802
valid_sources[0x67]	3903	1			T4	15		T9	15		T11	155
valid_sources[0x68]	3245	1			T4	18		T9	10		T12	2
valid_sources[0x69]	5210	1			T4	16		T9	10		T11	1724
valid_sources[0x6a]	4449	1			T4	7		T5	5		T9	9
valid_sources[0x6b]	3609	1			T4	15		T8	42		T9	10
valid_sources[0x6c]	4828	1			T4	7		T7	1032		T9	13
valid_sources[0x6d]	4562	1			T4	13		T8	35		T9	10
valid_sources[0x6e]	3305	1			T4	12		T8	8		T9	12
valid_sources[0x6f]	3793	1			T4	13		T8	10		T9	12
valid_sources[0x70]	4379	1			T4	11		T9	15		T12	2
valid_sources[0x71]	4638	1			T4	11		T9	8		T12	1
valid_sources[0x72]	4095	1			T4	13		T9	7		T11	70
valid_sources[0x73]	3839	1			T4	14		T9	9		T12	1
valid_sources[0x74]	3527	1			T4	15		T8	10		T9	17
valid_sources[0x75]	4553	1			T4	11		T9	9		T12	2
valid_sources[0x76]	4507	1			T4	21		T8	78		T9	12
valid_sources[0x77]	3313	1			T4	11		T9	12		T12	1
valid_sources[0x78]	3755	1			T4	10		T8	59		T9	7
valid_sources[0x79]	5209	1			T4	9		T9	13		T11	70
valid_sources[0x7a]	3499	1			T4	15		T8	140		T9	9
valid_sources[0x7b]	3917	1			T4	16		T9	5		T12	1
valid_sources[0x7c]	6443	1			T4	8		T9	12		T13	1
valid_sources[0x7d]	4218	1			T4	13		T5	369		T9	7
valid_sources[0x7e]	3754	1			T4	14		T9	13		T11	324
valid_sources[0x7f]	4226	1			T4	11		T9	6		T12	3
valid_sources[0x80]	3923	1			T4	13		T5	155		T9	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

267680

1

T4

671

T5

798

T6

222

values[0x0]

all_enables

biggest_size

87165

1

T2

1

T4

280

T5

244

values[0x1]

all_enables

biggest_size

46447

1

T2

1

T4

146

T5

99