Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11952549	14142	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11952549	130297	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11952549	7268554	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11952549	208505	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11952549	14142	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11952549	130297	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11952549	7268554	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11952549	208505	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	14142	0	0
T4	42175	75	0	0
T5	33093	39	0	0
T6	8429	0	0	0
T7	3232	0	0	0
T8	53214	75	0	0
T9	35832	29	0	0
T10	5300	0	0	0
T11	194828	247	0	0
T12	4562	4	0	0
T13	5782	4	0	0
T15	0	7	0	0
T24	0	33	0	0
T25	0	171	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	130297	0	0
T4	42175	715	0	0
T5	33093	351	0	0
T6	8429	0	0	0
T7	3232	0	0	0
T8	53214	700	0	0
T9	35832	271	0	0
T10	5300	0	0	0
T11	194828	2273	0	0
T12	4562	37	0	0
T13	5782	37	0	0
T15	0	63	0	0
T24	0	297	0	0
T25	0	1578	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	7268554	0	0
T1	2536	817	0	0
T2	1261	612	0	0
T3	5128	581	0	0
T4	42175	24723	0	0
T5	33093	23590	0	0
T6	8429	7803	0	0
T7	3232	2668	0	0
T8	53214	36023	0	0
T9	35832	27965	0	0
T10	5300	570	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	208505	0	0
T4	42175	1113	0	0
T5	33093	578	0	0
T6	8429	0	0	0
T7	3232	0	0	0
T8	53214	1095	0	0
T9	35832	430	0	0
T10	5300	0	0	0
T11	194828	3636	0	0
T12	4562	71	0	0
T13	5782	58	0	0
T15	0	103	0	0
T24	0	470	0	0
T25	0	2474	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	14142	0	0
T4	42175	75	0	0
T5	33093	39	0	0
T6	8429	0	0	0
T7	3232	0	0	0
T8	53214	75	0	0
T9	35832	29	0	0
T10	5300	0	0	0
T11	194828	247	0	0
T12	4562	4	0	0
T13	5782	4	0	0
T15	0	7	0	0
T24	0	33	0	0
T25	0	171	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	130297	0	0
T4	42175	715	0	0
T5	33093	351	0	0
T6	8429	0	0	0
T7	3232	0	0	0
T8	53214	700	0	0
T9	35832	271	0	0
T10	5300	0	0	0
T11	194828	2273	0	0
T12	4562	37	0	0
T13	5782	37	0	0
T15	0	63	0	0
T24	0	297	0	0
T25	0	1578	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	7268554	0	0
T1	2536	817	0	0
T2	1261	612	0	0
T3	5128	581	0	0
T4	42175	24723	0	0
T5	33093	23590	0	0
T6	8429	7803	0	0
T7	3232	2668	0	0
T8	53214	36023	0	0
T9	35832	27965	0	0
T10	5300	570	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	208505	0	0
T4	42175	1113	0	0
T5	33093	578	0	0
T6	8429	0	0	0
T7	3232	0	0	0
T8	53214	1095	0	0
T9	35832	430	0	0
T10	5300	0	0	0
T11	194828	3636	0	0
T12	4562	71	0	0
T13	5782	58	0	0
T15	0	103	0	0
T24	0	470	0	0
T25	0	2474	0	0