Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T11
0	1	Covered	T5,T9,T11
1	0	Covered	T5,T9,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T9,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56363190	8765	0	0
CascadeEffAonToRstPorAboveRise_A	56363190	8765	0	0
CascadeEffAonToRstPorIoAboveFall_A	54106535	8765	0	0
CascadeEffAonToRstPorIoAboveRise_A	54106535	8765	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27054237	8765	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27054237	8765	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13526804	8765	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13526804	8765	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27054357	8765	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27054357	8765	0	0
CascadeLcToLcAboveFall_A	56363190	22907	0	0
CascadeLcToLcAboveRise_A	56363190	22907	0	0
CascadeLcToLcAonAboveFall_A	1708979	22907	0	0
CascadeLcToLcAonAboveRise_A	1708979	22907	0	0
CascadeLcToLcShadowedAboveFall_A	56363190	22907	0	0
CascadeLcToLcShadowedAboveRise_A	56363190	22907	0	0
CascadePorToAonAboveFall_A	1708979	6690	0	0
CascadeSysToSysAboveFall_A	56363190	22907	0	0
CascadeSysToSysAboveRise_A	56363190	22907	0	0
ScanRstToAonRise_A	1708979	256	0	0
StablePorToAonRise_A	1708979	8765	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11952549	22907	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11952549	22907	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11952549	22907	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11952549	22907	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13526804	22907	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13526804	22907	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11952549	22907	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11952549	22907	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11952549	22907	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11952549	22907	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	8765	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	27	0	0
T5	163897	21	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	27	0	0
T9	169497	20	0	0
T10	24355	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	8765	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	27	0	0
T5	163897	21	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	27	0	0
T9	169497	20	0	0
T10	24355	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106535	8765	0	0
T1	10701	2	0	0
T2	5121	1	0	0
T3	23453	8	0	0
T4	180714	27	0	0
T5	157356	21	0	0
T6	33888	1	0	0
T7	13296	1	0	0
T8	226742	27	0	0
T9	162691	20	0	0
T10	23387	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106535	8765	0	0
T1	10701	2	0	0
T2	5121	1	0	0
T3	23453	8	0	0
T4	180714	27	0	0
T5	157356	21	0	0
T6	33888	1	0	0
T7	13296	1	0	0
T8	226742	27	0	0
T9	162691	20	0	0
T10	23387	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054237	8765	0	0
T1	5350	2	0	0
T2	2561	1	0	0
T3	11733	8	0	0
T4	90338	27	0	0
T5	78677	21	0	0
T6	16943	1	0	0
T7	6647	1	0	0
T8	113371	27	0	0
T9	81367	20	0	0
T10	11696	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054237	8765	0	0
T1	5350	2	0	0
T2	2561	1	0	0
T3	11733	8	0	0
T4	90338	27	0	0
T5	78677	21	0	0
T6	16943	1	0	0
T7	6647	1	0	0
T8	113371	27	0	0
T9	81367	20	0	0
T10	11696	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	8765	0	0
T1	2674	2	0	0
T2	1278	1	0	0
T3	5862	8	0	0
T4	45177	27	0	0
T5	39338	21	0	0
T6	8470	1	0	0
T7	3323	1	0	0
T8	56684	27	0	0
T9	40679	20	0	0
T10	5843	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	8765	0	0
T1	2674	2	0	0
T2	1278	1	0	0
T3	5862	8	0	0
T4	45177	27	0	0
T5	39338	21	0	0
T6	8470	1	0	0
T7	3323	1	0	0
T8	56684	27	0	0
T9	40679	20	0	0
T10	5843	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054357	8765	0	0
T1	5350	2	0	0
T2	2561	1	0	0
T3	11737	8	0	0
T4	90344	27	0	0
T5	78683	21	0	0
T6	16944	1	0	0
T7	6647	1	0	0
T8	113373	27	0	0
T9	81367	20	0	0
T10	11691	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054357	8765	0	0
T1	5350	2	0	0
T2	2561	1	0	0
T3	11737	8	0	0
T4	90344	27	0	0
T5	78683	21	0	0
T6	16944	1	0	0
T7	6647	1	0	0
T8	113373	27	0	0
T9	81367	20	0	0
T10	11691	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	22907	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	102	0	0
T5	163897	60	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	102	0	0
T9	169497	49	0	0
T10	24355	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	22907	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	102	0	0
T5	163897	60	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	102	0	0
T9	169497	49	0	0
T10	24355	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	22907	0	0
T1	333	2	0	0
T2	158	1	0	0
T3	734	8	0	0
T4	5661	102	0	0
T5	4986	60	0	0
T6	1057	1	0	0
T7	415	1	0	0
T8	7100	102	0	0
T9	5164	49	0	0
T10	732	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	22907	0	0
T1	333	2	0	0
T2	158	1	0	0
T3	734	8	0	0
T4	5661	102	0	0
T5	4986	60	0	0
T6	1057	1	0	0
T7	415	1	0	0
T8	7100	102	0	0
T9	5164	49	0	0
T10	732	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	22907	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	102	0	0
T5	163897	60	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	102	0	0
T9	169497	49	0	0
T10	24355	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	22907	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	102	0	0
T5	163897	60	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	102	0	0
T9	169497	49	0	0
T10	24355	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	6690	0	0
T1	333	6	0	0
T2	158	1	0	0
T3	734	8	0	0
T4	5661	27	0	0
T5	4986	10	0	0
T6	1057	1	0	0
T7	415	1	0	0
T8	7100	27	0	0
T9	5164	5	0	0
T10	732	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	22907	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	102	0	0
T5	163897	60	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	102	0	0
T9	169497	49	0	0
T10	24355	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56363190	22907	0	0
T1	11148	2	0	0
T2	5335	1	0	0
T3	24445	8	0	0
T4	188194	102	0	0
T5	163897	60	0	0
T6	35301	1	0	0
T7	13851	1	0	0
T8	236194	102	0	0
T9	169497	49	0	0
T10	24355	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	256	0	0
T5	4986	1	0	0
T6	1057	0	0	0
T7	415	0	0	0
T8	7100	0	0	0
T9	5164	0	0	0
T10	732	0	0	0
T11	28308	5	0	0
T12	581	0	0	0
T13	763	0	0	0
T14	260	0	0	0
T25	0	5	0	0
T41	0	1	0	0
T80	0	1	0	0
T87	0	1	0	0
T101	0	3	0	0
T102	0	1	0	0
T108	0	1	0	0
T137	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	8765	0	0
T1	333	2	0	0
T2	158	1	0	0
T3	734	8	0	0
T4	5661	27	0	0
T5	4986	21	0	0
T6	1057	1	0	0
T7	415	1	0	0
T8	7100	27	0	0
T9	5164	20	0	0
T10	732	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	22907	0	0
T1	2674	2	0	0
T2	1278	1	0	0
T3	5862	8	0	0
T4	45177	102	0	0
T5	39338	60	0	0
T6	8470	1	0	0
T7	3323	1	0	0
T8	56684	102	0	0
T9	40679	49	0	0
T10	5843	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	22907	0	0
T1	2674	2	0	0
T2	1278	1	0	0
T3	5862	8	0	0
T4	45177	102	0	0
T5	39338	60	0	0
T6	8470	1	0	0
T7	3323	1	0	0
T8	56684	102	0	0
T9	40679	49	0	0
T10	5843	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11952549	22907	0	0
T1	2536	2	0	0
T2	1261	1	0	0
T3	5128	8	0	0
T4	42175	102	0	0
T5	33093	60	0	0
T6	8429	1	0	0
T7	3232	1	0	0
T8	53214	102	0	0
T9	35832	49	0	0
T10	5300	8	0	0