Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13526804	15165	0	0
gen_assertions[0].RstEnOn_A	13526804	1213	0	0
gen_assertions[0].RstNOff_A	13526804	15165	0	0
gen_assertions[0].RstNOn_A	13526804	1213	0	0
gen_assertions[1].RstEnOff_A	54106535	13835	0	0
gen_assertions[1].RstEnOn_A	54106535	1187	0	0
gen_assertions[1].RstNOff_A	54106535	13835	0	0
gen_assertions[1].RstNOn_A	54106535	1187	0	0
gen_assertions[2].RstEnOff_A	27054237	13895	0	0
gen_assertions[2].RstEnOn_A	27054237	1169	0	0
gen_assertions[2].RstNOff_A	27054237	13895	0	0
gen_assertions[2].RstNOn_A	27054237	1169	0	0
gen_assertions[3].RstEnOff_A	27054357	13937	0	0
gen_assertions[3].RstEnOn_A	27054357	1204	0	0
gen_assertions[3].RstNOff_A	27054357	13937	0	0
gen_assertions[3].RstNOn_A	27054357	1204	0	0
gen_assertions[4].RstEnOff_A	1708979	22788	0	0
gen_assertions[4].RstEnOn_A	1708979	1246	0	0
gen_assertions[4].RstNOff_A	1708979	22788	0	0
gen_assertions[4].RstNOn_A	1708979	1246	0	0
gen_assertions[5].RstEnOff_A	13526804	15399	0	0
gen_assertions[5].RstEnOn_A	13526804	1302	0	0
gen_assertions[5].RstNOff_A	13526804	15399	0	0
gen_assertions[5].RstNOn_A	13526804	1302	0	0
gen_assertions[6].RstEnOff_A	13526804	15444	0	0
gen_assertions[6].RstEnOn_A	13526804	1340	0	0
gen_assertions[6].RstNOff_A	13526804	15444	0	0
gen_assertions[6].RstNOn_A	13526804	1340	0	0
gen_assertions[7].RstEnOff_A	13526804	15492	0	0
gen_assertions[7].RstEnOn_A	13526804	1398	0	0
gen_assertions[7].RstNOff_A	13526804	15492	0	0
gen_assertions[7].RstNOn_A	13526804	1398	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15165	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	1	0	0
T7	3323	7	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	278	0	0
T12	4661	5	0	0
T13	6119	5	0	0
T15	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1213	0	0
T6	8470	1	0	0
T7	3323	7	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	31	0	0
T12	4661	1	0	0
T13	6119	1	0	0
T14	2093	0	0	0
T15	0	4	0	0
T25	0	20	0	0
T40	1751	0	0	0
T62	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15165	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	1	0	0
T7	3323	7	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	278	0	0
T12	4661	5	0	0
T13	6119	5	0	0
T15	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1213	0	0
T6	8470	1	0	0
T7	3323	7	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	31	0	0
T12	4661	1	0	0
T13	6119	1	0	0
T14	2093	0	0	0
T15	0	4	0	0
T25	0	20	0	0
T40	1751	0	0	0
T62	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106535	13835	0	0
T4	180714	67	0	0
T5	157356	37	0	0
T6	33888	3	0	0
T7	13296	7	0	0
T8	226742	65	0	0
T9	162691	25	0	0
T10	23387	0	0	0
T11	890726	262	0	0
T12	18645	4	0	0
T13	24483	5	0	0
T15	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106535	1187	0	0
T6	33888	3	0	0
T7	13296	7	0	0
T8	226742	0	0	0
T9	162691	0	0	0
T10	23387	0	0	0
T11	890726	36	0	0
T12	18645	0	0	0
T13	24483	1	0	0
T14	8374	0	0	0
T15	0	3	0	0
T25	0	17	0	0
T40	7011	0	0	0
T43	0	7	0	0
T84	0	1	0	0
T85	0	4	0	0
T86	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106535	13835	0	0
T4	180714	67	0	0
T5	157356	37	0	0
T6	33888	3	0	0
T7	13296	7	0	0
T8	226742	65	0	0
T9	162691	25	0	0
T10	23387	0	0	0
T11	890726	262	0	0
T12	18645	4	0	0
T13	24483	5	0	0
T15	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54106535	1187	0	0
T6	33888	3	0	0
T7	13296	7	0	0
T8	226742	0	0	0
T9	162691	0	0	0
T10	23387	0	0	0
T11	890726	36	0	0
T12	18645	0	0	0
T13	24483	1	0	0
T14	8374	0	0	0
T15	0	3	0	0
T25	0	17	0	0
T40	7011	0	0	0
T43	0	7	0	0
T84	0	1	0	0
T85	0	4	0	0
T86	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054237	13895	0	0
T4	90338	67	0	0
T5	78677	37	0	0
T6	16943	4	0	0
T7	6647	7	0	0
T8	113371	65	0	0
T9	81367	25	0	0
T10	11696	0	0	0
T11	445415	261	0	0
T12	9324	5	0	0
T13	12239	5	0	0
T15	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054237	1169	0	0
T6	16943	4	0	0
T7	6647	7	0	0
T8	113371	0	0	0
T9	81367	0	0	0
T10	11696	0	0	0
T11	445415	35	0	0
T12	9324	1	0	0
T13	12239	1	0	0
T14	4187	0	0	0
T25	0	18	0	0
T40	3505	0	0	0
T43	0	5	0	0
T51	0	1	0	0
T84	0	1	0	0
T85	0	5	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054237	13895	0	0
T4	90338	67	0	0
T5	78677	37	0	0
T6	16943	4	0	0
T7	6647	7	0	0
T8	113371	65	0	0
T9	81367	25	0	0
T10	11696	0	0	0
T11	445415	261	0	0
T12	9324	5	0	0
T13	12239	5	0	0
T15	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054237	1169	0	0
T6	16943	4	0	0
T7	6647	7	0	0
T8	113371	0	0	0
T9	81367	0	0	0
T10	11696	0	0	0
T11	445415	35	0	0
T12	9324	1	0	0
T13	12239	1	0	0
T14	4187	0	0	0
T25	0	18	0	0
T40	3505	0	0	0
T43	0	5	0	0
T51	0	1	0	0
T84	0	1	0	0
T85	0	5	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054357	13937	0	0
T4	90344	67	0	0
T5	78683	37	0	0
T6	16944	5	0	0
T7	6647	9	0	0
T8	113373	65	0	0
T9	81367	25	0	0
T10	11691	0	0	0
T11	445405	257	0	0
T12	9321	4	0	0
T13	12240	4	0	0
T15	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054357	1204	0	0
T6	16944	5	0	0
T7	6647	9	0	0
T8	113373	0	0	0
T9	81367	0	0	0
T10	11691	0	0	0
T11	445405	31	0	0
T12	9321	0	0	0
T13	12240	0	0	0
T14	4188	0	0	0
T25	0	21	0	0
T40	3506	0	0	0
T43	0	10	0	0
T52	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T85	0	6	0	0
T87	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054357	13937	0	0
T4	90344	67	0	0
T5	78683	37	0	0
T6	16944	5	0	0
T7	6647	9	0	0
T8	113373	65	0	0
T9	81367	25	0	0
T10	11691	0	0	0
T11	445405	257	0	0
T12	9321	4	0	0
T13	12240	4	0	0
T15	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27054357	1204	0	0
T6	16944	5	0	0
T7	6647	9	0	0
T8	113373	0	0	0
T9	81367	0	0	0
T10	11691	0	0	0
T11	445405	31	0	0
T12	9321	0	0	0
T13	12240	0	0	0
T14	4188	0	0	0
T25	0	21	0	0
T40	3506	0	0	0
T43	0	10	0	0
T52	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T85	0	6	0	0
T87	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	22788	0	0
T1	333	2	0	0
T2	158	1	0	0
T3	734	3	0	0
T4	5661	89	0	0
T5	4986	59	0	0
T6	1057	7	0	0
T7	415	11	0	0
T8	7100	100	0	0
T9	5164	48	0	0
T10	732	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	1246	0	0
T6	1057	6	0	0
T7	415	10	0	0
T8	7100	0	0	0
T9	5164	0	0	0
T10	732	0	0	0
T11	28308	33	0	0
T12	581	0	0	0
T13	763	0	0	0
T14	260	0	0	0
T25	0	23	0	0
T40	217	0	0	0
T43	0	11	0	0
T52	0	7	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	8	0	0
T88	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	22788	0	0
T1	333	2	0	0
T2	158	1	0	0
T3	734	3	0	0
T4	5661	89	0	0
T5	4986	59	0	0
T6	1057	7	0	0
T7	415	11	0	0
T8	7100	100	0	0
T9	5164	48	0	0
T10	732	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708979	1246	0	0
T6	1057	6	0	0
T7	415	10	0	0
T8	7100	0	0	0
T9	5164	0	0	0
T10	732	0	0	0
T11	28308	33	0	0
T12	581	0	0	0
T13	763	0	0	0
T14	260	0	0	0
T25	0	23	0	0
T40	217	0	0	0
T43	0	11	0	0
T52	0	7	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	8	0	0
T88	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15399	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	6	0	0
T7	3323	12	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	281	0	0
T12	4661	4	0	0
T13	6119	5	0	0
T15	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1302	0	0
T6	8470	6	0	0
T7	3323	12	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	34	0	0
T12	4661	0	0	0
T13	6119	1	0	0
T14	2093	0	0	0
T25	0	18	0	0
T40	1751	0	0	0
T43	0	9	0	0
T52	0	11	0	0
T84	0	2	0	0
T85	0	8	0	0
T88	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15399	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	6	0	0
T7	3323	12	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	281	0	0
T12	4661	4	0	0
T13	6119	5	0	0
T15	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1302	0	0
T6	8470	6	0	0
T7	3323	12	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	34	0	0
T12	4661	0	0	0
T13	6119	1	0	0
T14	2093	0	0	0
T25	0	18	0	0
T40	1751	0	0	0
T43	0	9	0	0
T52	0	11	0	0
T84	0	2	0	0
T85	0	8	0	0
T88	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15444	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	8	0	0
T7	3323	12	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	284	0	0
T12	4661	4	0	0
T13	6119	5	0	0
T15	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1340	0	0
T6	8470	8	0	0
T7	3323	12	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	37	0	0
T12	4661	0	0	0
T13	6119	1	0	0
T14	2093	0	0	0
T25	0	23	0	0
T40	1751	0	0	0
T43	0	11	0	0
T52	0	10	0	0
T84	0	1	0	0
T85	0	9	0	0
T88	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15444	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	8	0	0
T7	3323	12	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	284	0	0
T12	4661	4	0	0
T13	6119	5	0	0
T15	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1340	0	0
T6	8470	8	0	0
T7	3323	12	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	37	0	0
T12	4661	0	0	0
T13	6119	1	0	0
T14	2093	0	0	0
T25	0	23	0	0
T40	1751	0	0	0
T43	0	11	0	0
T52	0	10	0	0
T84	0	1	0	0
T85	0	9	0	0
T88	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15492	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	9	0	0
T7	3323	13	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	274	0	0
T12	4661	4	0	0
T13	6119	4	0	0
T15	0	7	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1398	0	0
T6	8470	9	0	0
T7	3323	13	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	28	0	0
T12	4661	0	0	0
T13	6119	0	0	0
T14	2093	0	0	0
T25	0	17	0	0
T40	1751	0	0	0
T43	0	11	0	0
T52	0	12	0	0
T84	0	1	0	0
T85	0	10	0	0
T88	0	10	0	0
T89	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	15492	0	0
T4	45177	75	0	0
T5	39338	39	0	0
T6	8470	9	0	0
T7	3323	13	0	0
T8	56684	75	0	0
T9	40679	29	0	0
T10	5843	0	0	0
T11	222700	274	0	0
T12	4661	4	0	0
T13	6119	4	0	0
T15	0	7	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13526804	1398	0	0
T6	8470	9	0	0
T7	3323	13	0	0
T8	56684	0	0	0
T9	40679	0	0	0
T10	5843	0	0	0
T11	222700	28	0	0
T12	4661	0	0	0
T13	6119	0	0	0
T14	2093	0	0	0
T25	0	17	0	0
T40	1751	0	0	0
T43	0	11	0	0
T52	0	12	0	0
T84	0	1	0	0
T85	0	10	0	0
T88	0	10	0	0
T89	0	1	0	0