Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12730698	9921	0	0
alert_regwen_rd_A	12730698	4077	0	0
cpu_regwen_rd_A	12730698	4388	0	0
sw_rst_ctrl_n_0_rd_A	12730698	9003	0	0
sw_rst_ctrl_n_1_rd_A	12730698	8980	0	0
sw_rst_ctrl_n_2_rd_A	12730698	9179	0	0
sw_rst_ctrl_n_3_rd_A	12730698	9126	0	0
sw_rst_ctrl_n_4_rd_A	12730698	9273	0	0
sw_rst_ctrl_n_5_rd_A	12730698	9147	0	0
sw_rst_ctrl_n_6_rd_A	12730698	9036	0	0
sw_rst_ctrl_n_7_rd_A	12730698	9109	0	0
sw_rst_regwen_0_rd_A	12730698	4809	0	0
sw_rst_regwen_1_rd_A	12730698	4871	0	0
sw_rst_regwen_2_rd_A	12730698	4817	0	0
sw_rst_regwen_3_rd_A	12730698	4876	0	0
sw_rst_regwen_4_rd_A	12730698	4661	0	0
sw_rst_regwen_5_rd_A	12730698	4791	0	0
sw_rst_regwen_6_rd_A	12730698	4811	0	0
sw_rst_regwen_7_rd_A	12730698	4948	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9921	0	0
T63	3008	35	0	0
T64	4205	167	0	0
T65	2682	177	0	0
T66	10528	1	0	0
T68	3862	88	0	0
T92	3231	19	0	0
T93	21607	1	0	0
T94	3340	16	0	0
T95	3574	61	0	0
T96	10189	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4077	0	0
T9	35832	52	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	0	0	0
T14	1978	0	0	0
T15	1708	0	0	0
T24	11895	0	0	0
T25	184652	260	0	0
T40	1710	0	0	0
T80	0	40	0	0
T107	0	297	0	0
T127	0	66	0	0
T128	0	69	0	0
T129	0	29	0	0
T130	0	108	0	0
T131	0	64	0	0
T132	0	28	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4388	0	0
T9	35832	75	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	0	0	0
T14	1978	0	0	0
T15	1708	0	0	0
T24	11895	0	0	0
T25	184652	231	0	0
T40	1710	0	0	0
T80	0	48	0	0
T107	0	250	0	0
T127	0	57	0	0
T128	0	54	0	0
T129	0	40	0	0
T130	0	94	0	0
T131	0	63	0	0
T132	0	45	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9003	0	0
T6	8429	83	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	88	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	14	0	0
T14	1978	0	0	0
T25	0	540	0	0
T40	1710	0	0	0
T52	0	159	0	0
T80	0	59	0	0
T82	0	36	0	0
T127	0	64	0	0
T133	0	60	0	0
T134	0	7	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	8980	0	0
T6	8429	60	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	60	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	23	0	0
T14	1978	0	0	0
T25	0	482	0	0
T40	1710	0	0	0
T52	0	199	0	0
T80	0	56	0	0
T82	0	51	0	0
T127	0	80	0	0
T133	0	63	0	0
T134	0	2	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9179	0	0
T6	8429	79	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	92	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	22	0	0
T14	1978	0	0	0
T25	0	493	0	0
T40	1710	0	0	0
T52	0	144	0	0
T80	0	45	0	0
T82	0	55	0	0
T127	0	57	0	0
T133	0	76	0	0
T134	0	19	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9126	0	0
T6	8429	89	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	75	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	11	0	0
T14	1978	0	0	0
T25	0	479	0	0
T40	1710	0	0	0
T52	0	155	0	0
T80	0	49	0	0
T82	0	34	0	0
T127	0	48	0	0
T133	0	87	0	0
T134	0	14	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9273	0	0
T6	8429	77	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	63	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	10	0	0
T14	1978	0	0	0
T25	0	516	0	0
T40	1710	0	0	0
T52	0	171	0	0
T80	0	49	0	0
T82	0	37	0	0
T127	0	59	0	0
T133	0	72	0	0
T134	0	5	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9147	0	0
T6	8429	105	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	83	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	17	0	0
T14	1978	0	0	0
T25	0	439	0	0
T40	1710	0	0	0
T52	0	161	0	0
T80	0	42	0	0
T82	0	45	0	0
T127	0	67	0	0
T133	0	78	0	0
T134	0	13	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9036	0	0
T6	8429	91	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	70	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	14	0	0
T14	1978	0	0	0
T25	0	535	0	0
T40	1710	0	0	0
T52	0	134	0	0
T80	0	66	0	0
T82	0	39	0	0
T127	0	75	0	0
T133	0	52	0	0
T134	0	9	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	9109	0	0
T6	8429	79	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	60	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	9	0	0
T14	1978	0	0	0
T25	0	499	0	0
T40	1710	0	0	0
T52	0	182	0	0
T80	0	32	0	0
T82	0	34	0	0
T127	0	65	0	0
T133	0	77	0	0
T134	0	16	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4809	0	0
T6	8429	26	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	70	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	8	0	0
T14	1978	0	0	0
T25	0	272	0	0
T40	1710	0	0	0
T52	0	39	0	0
T80	0	41	0	0
T107	0	285	0	0
T127	0	64	0	0
T128	0	64	0	0
T135	0	10	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4871	0	0
T6	8429	20	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	61	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	9	0	0
T14	1978	0	0	0
T25	0	210	0	0
T40	1710	0	0	0
T52	0	34	0	0
T80	0	61	0	0
T107	0	282	0	0
T127	0	78	0	0
T128	0	66	0	0
T135	0	9	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4817	0	0
T6	8429	13	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	75	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	3	0	0
T14	1978	0	0	0
T25	0	247	0	0
T40	1710	0	0	0
T52	0	30	0	0
T80	0	45	0	0
T127	0	86	0	0
T128	0	94	0	0
T134	0	5	0	0
T135	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4876	0	0
T6	8429	15	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	76	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	9	0	0
T14	1978	0	0	0
T25	0	249	0	0
T40	1710	0	0	0
T52	0	19	0	0
T80	0	51	0	0
T127	0	67	0	0
T128	0	72	0	0
T134	0	5	0	0
T135	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4661	0	0
T6	8429	13	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	68	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	4	0	0
T14	1978	0	0	0
T25	0	226	0	0
T40	1710	0	0	0
T52	0	35	0	0
T80	0	33	0	0
T127	0	51	0	0
T128	0	75	0	0
T134	0	1	0	0
T135	0	15	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4791	0	0
T6	8429	3	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	67	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	0	0	0
T14	1978	0	0	0
T25	0	226	0	0
T40	1710	0	0	0
T52	0	30	0	0
T80	0	38	0	0
T107	0	274	0	0
T127	0	67	0	0
T128	0	92	0	0
T129	0	34	0	0
T134	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4811	0	0
T6	8429	20	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	48	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	9	0	0
T14	1978	0	0	0
T25	0	260	0	0
T40	1710	0	0	0
T52	0	32	0	0
T80	0	65	0	0
T127	0	36	0	0
T128	0	71	0	0
T134	0	5	0	0
T135	0	10	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12730698	4948	0	0
T6	8429	13	0	0
T7	3232	0	0	0
T8	53214	0	0	0
T9	35832	66	0	0
T10	5300	0	0	0
T11	194828	0	0	0
T12	4562	0	0	0
T13	5782	10	0	0
T14	1978	0	0	0
T25	0	244	0	0
T40	1710	0	0	0
T52	0	32	0	0
T80	0	48	0	0
T127	0	48	0	0
T128	0	72	0	0
T134	0	8	0	0
T135	0	12	0	0