RSTMGR Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.710s 234.453us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.920s 145.289us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.940s 72.577us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.340s 1.555ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 1.830s 152.531us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.800s 187.248us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.940s 72.577us 20 20 100.00
rstmgr_csr_aliasing 1.830s 152.531us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.000s 251.251us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.880s 495.330us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.600s 299.787us 50 50 100.00
V2 reset_info rstmgr_reset 8.290s 2.005ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.290s 2.005ms 50 50 100.00
V2 alert_info rstmgr_reset 8.290s 2.005ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.290s 2.005ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.010m 16.872ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.890s 72.233us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.390s 607.207us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.390s 607.207us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.920s 145.289us 5 5 100.00
rstmgr_csr_rw 0.940s 72.577us 20 20 100.00
rstmgr_csr_aliasing 1.830s 152.531us 5 5 100.00
rstmgr_same_csr_outstanding 1.620s 265.040us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.920s 145.289us 5 5 100.00
rstmgr_csr_rw 0.940s 72.577us 20 20 100.00
rstmgr_csr_aliasing 1.830s 152.531us 5 5 100.00
rstmgr_same_csr_outstanding 1.620s 265.040us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 24.370s 16.683ms 5 5 100.00
rstmgr_tl_intg_err 3.380s 882.238us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 24.370s 16.683ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 24.370s 16.683ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.380s 882.238us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.320s 179.274us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.320s 2.348ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.200s 244.538us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 24.370s 16.683ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.940s 72.577us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.940s 72.577us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.40 99.40 99.31 99.87 -- 99.83 99.46 98.52

Past Results