Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616750	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

369782

1

T1

987

T2

56

T3

349

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526452	1			T1	1454		T2	90		T3	491
values[0x0]	229831	1			T1	633		T2	41		T3	213
values[0x1]	230249	1			T1	598		T2	53		T3	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	517484	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

469048

1

T1

1273

T2

75

T3

440

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3986	1			T1	1		T3	3		T5	10
valid_sources[0x01]	3516	1			T3	2		T8	10		T11	2
valid_sources[0x02]	3039	1			T3	8		T8	12		T11	1
valid_sources[0x03]	3337	1			T3	1		T4	31		T5	20
valid_sources[0x04]	3160	1			T3	3		T8	12		T11	6
valid_sources[0x05]	4099	1			T1	141		T2	1		T3	8
valid_sources[0x06]	3111	1			T1	11		T8	18		T11	3
valid_sources[0x07]	3568	1			T3	4		T8	14		T10	197
valid_sources[0x08]	3196	1			T3	3		T5	7		T8	6
valid_sources[0x09]	3205	1			T3	4		T8	8		T10	178
valid_sources[0x0a]	3563	1			T4	99		T8	14		T11	3
valid_sources[0x0b]	4223	1			T3	1		T8	13		T11	7
valid_sources[0x0c]	2964	1			T3	6		T5	9		T8	12
valid_sources[0x0d]	4488	1			T2	6		T3	2		T5	2
valid_sources[0x0e]	3534	1			T3	3		T8	13		T9	1
valid_sources[0x0f]	3855	1			T3	3		T8	13		T11	6
valid_sources[0x10]	3210	1			T3	1		T8	9		T9	1
valid_sources[0x11]	3692	1			T1	57		T3	1		T8	12
valid_sources[0x12]	3601	1			T3	5		T8	13		T11	9
valid_sources[0x13]	2917	1			T3	9		T8	10		T11	2
valid_sources[0x14]	4331	1			T2	4		T8	10		T10	113
valid_sources[0x15]	4406	1			T3	1		T5	5		T8	7
valid_sources[0x16]	5455	1			T1	5		T3	6		T8	14
valid_sources[0x17]	3511	1			T3	6		T8	8		T10	12
valid_sources[0x18]	4107	1			T3	3		T5	2		T8	10
valid_sources[0x19]	3134	1			T5	2		T8	14		T13	8
valid_sources[0x1a]	3116	1			T1	496		T3	4		T8	14
valid_sources[0x1b]	3855	1			T3	1		T8	5		T9	1
valid_sources[0x1c]	3407	1			T3	4		T8	10		T11	5
valid_sources[0x1d]	4726	1			T2	3		T5	1		T8	11
valid_sources[0x1e]	4826	1			T3	4		T8	9		T11	4
valid_sources[0x1f]	3365	1			T3	1		T8	19		T10	279
valid_sources[0x20]	2875	1			T8	7		T11	9		T16	1
valid_sources[0x21]	3209	1			T3	8		T5	2		T8	8
valid_sources[0x22]	4265	1			T3	2		T8	16		T10	197
valid_sources[0x23]	6123	1			T2	4		T3	9		T8	19
valid_sources[0x24]	6979	1			T3	3		T8	14		T9	1
valid_sources[0x25]	4192	1			T3	4		T5	2		T8	13
valid_sources[0x26]	2956	1			T3	3		T8	10		T11	5
valid_sources[0x27]	4002	1			T3	4		T8	16		T10	273
valid_sources[0x28]	4047	1			T3	4		T8	18		T11	2
valid_sources[0x29]	4528	1			T3	3		T8	13		T10	9
valid_sources[0x2a]	4781	1			T3	6		T8	9		T11	3
valid_sources[0x2b]	2988	1			T3	5		T8	11		T13	2
valid_sources[0x2c]	4326	1			T8	16		T10	711		T11	14
valid_sources[0x2d]	3279	1			T3	6		T8	14		T66	1
valid_sources[0x2e]	3996	1			T3	1		T5	4		T8	12
valid_sources[0x2f]	3442	1			T3	3		T8	20		T11	8
valid_sources[0x30]	3139	1			T3	1		T5	13		T8	13
valid_sources[0x31]	3898	1			T3	1		T8	6		T9	1
valid_sources[0x32]	3261	1			T3	2		T8	11		T11	7
valid_sources[0x33]	4945	1			T8	10		T11	1		T13	2
valid_sources[0x34]	7335	1			T2	1		T3	4		T8	9
valid_sources[0x35]	3531	1			T1	317		T3	1		T8	13
valid_sources[0x36]	3251	1			T3	7		T8	11		T10	13
valid_sources[0x37]	3762	1			T3	2		T8	15		T9	1
valid_sources[0x38]	3297	1			T3	4		T5	2		T8	10
valid_sources[0x39]	3910	1			T3	1		T8	12		T11	3
valid_sources[0x3a]	2910	1			T3	2		T8	14		T11	3
valid_sources[0x3b]	4866	1			T3	4		T5	7		T8	19
valid_sources[0x3c]	3455	1			T3	1		T8	11		T9	1
valid_sources[0x3d]	3252	1			T2	1		T3	8		T4	66
valid_sources[0x3e]	3550	1			T1	240		T3	3		T5	2
valid_sources[0x3f]	3974	1			T1	5		T3	3		T5	1
valid_sources[0x40]	3823	1			T3	3		T8	10		T11	1
valid_sources[0x41]	3062	1			T3	3		T8	12		T13	62
valid_sources[0x42]	3301	1			T3	8		T4	3		T8	7
valid_sources[0x43]	3738	1			T3	3		T5	1		T8	17
valid_sources[0x44]	2967	1			T3	3		T8	12		T10	117
valid_sources[0x45]	4714	1			T3	3		T8	12		T10	120
valid_sources[0x46]	3722	1			T3	5		T5	4		T8	10
valid_sources[0x47]	2894	1			T3	8		T8	15		T11	9
valid_sources[0x48]	4795	1			T3	2		T4	40		T8	7
valid_sources[0x49]	3340	1			T2	12		T3	2		T8	18
valid_sources[0x4a]	3369	1			T3	5		T5	7		T8	11
valid_sources[0x4b]	3308	1			T3	1		T8	11		T11	5
valid_sources[0x4c]	3803	1			T3	5		T8	14		T11	3
valid_sources[0x4d]	2959	1			T3	2		T8	9		T9	1
valid_sources[0x4e]	3067	1			T3	4		T8	16		T11	4
valid_sources[0x4f]	2618	1			T3	2		T8	18		T11	7
valid_sources[0x50]	3893	1			T2	7		T3	6		T8	20
valid_sources[0x51]	3596	1			T3	11		T8	19		T9	1
valid_sources[0x52]	3099	1			T3	6		T5	1		T8	13
valid_sources[0x53]	3783	1			T3	3		T5	11		T8	16
valid_sources[0x54]	4131	1			T3	8		T4	75		T5	3
valid_sources[0x55]	3482	1			T3	3		T8	13		T10	103
valid_sources[0x56]	3420	1			T2	9		T3	4		T4	9
valid_sources[0x57]	5650	1			T3	4		T8	22		T9	1
valid_sources[0x58]	2531	1			T3	6		T8	15		T11	3
valid_sources[0x59]	3725	1			T3	9		T5	1		T8	10
valid_sources[0x5a]	7140	1			T1	69		T3	5		T8	9
valid_sources[0x5b]	4049	1			T3	2		T5	3		T8	7
valid_sources[0x5c]	3786	1			T3	3		T5	2		T8	12
valid_sources[0x5d]	3186	1			T2	6		T3	4		T5	1
valid_sources[0x5e]	4485	1			T3	3		T5	6		T8	6
valid_sources[0x5f]	3370	1			T1	113		T3	4		T8	6
valid_sources[0x60]	4456	1			T3	3		T8	8		T11	4
valid_sources[0x61]	3491	1			T3	4		T5	1		T8	13
valid_sources[0x62]	4154	1			T8	14		T11	6		T13	3
valid_sources[0x63]	3035	1			T3	4		T5	3		T8	17
valid_sources[0x64]	2945	1			T3	7		T8	11		T10	5
valid_sources[0x65]	3844	1			T3	3		T5	6		T8	7
valid_sources[0x66]	3680	1			T3	7		T5	1		T8	7
valid_sources[0x67]	3839	1			T2	6		T3	3		T8	6
valid_sources[0x68]	3931	1			T3	2		T8	15		T11	4
valid_sources[0x69]	3160	1			T3	3		T8	18		T11	1
valid_sources[0x6a]	3402	1			T3	3		T8	11		T66	1
valid_sources[0x6b]	3380	1			T3	8		T8	13		T11	3
valid_sources[0x6c]	5722	1			T3	5		T8	10		T11	9
valid_sources[0x6d]	3373	1			T3	2		T8	11		T11	3
valid_sources[0x6e]	3349	1			T3	2		T8	15		T9	1
valid_sources[0x6f]	4326	1			T3	1		T6	808		T8	15
valid_sources[0x70]	3602	1			T3	1		T5	8		T8	15
valid_sources[0x71]	3122	1			T1	4		T3	5		T8	11
valid_sources[0x72]	6730	1			T2	11		T8	9		T11	1
valid_sources[0x73]	3612	1			T3	2		T8	13		T11	8
valid_sources[0x74]	3408	1			T5	7		T8	8		T11	7
valid_sources[0x75]	3302	1			T2	6		T3	4		T8	13
valid_sources[0x76]	4234	1			T3	5		T4	28		T8	14
valid_sources[0x77]	4260	1			T1	1		T3	6		T8	8
valid_sources[0x78]	3883	1			T2	3		T3	8		T4	30
valid_sources[0x79]	4010	1			T3	6		T8	12		T10	60
valid_sources[0x7a]	2968	1			T3	1		T8	21		T11	5
valid_sources[0x7b]	4162	1			T3	3		T8	9		T11	2
valid_sources[0x7c]	3064	1			T2	1		T3	5		T8	9
valid_sources[0x7d]	4220	1			T3	8		T8	6		T11	5
valid_sources[0x7e]	3394	1			T1	7		T3	2		T5	5
valid_sources[0x7f]	4353	1			T3	4		T5	7		T8	10
valid_sources[0x80]	4511	1			T3	5		T5	3		T8	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

246873

1

T1

666

T2

33

T3

235

values[0x0]

all_enables

biggest_size

80239

1

T1

219

T2

14

T3

67

values[0x1]

all_enables

biggest_size

42670

1

T1

102

T2

9

T3

47