| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 58.33 | 1 | 100 | 1 | 1 | 64 | 64 | 
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val | 16.67 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 16.67 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 5 | 1 | 16.67 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 5 | 1 | 16.67 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 5 | 1 | 16.67 | 
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| others[0] | 0 | 1 | 1 | |
| others[1] | 0 | 1 | 1 | |
| others[2] | 0 | 1 | 1 | |
| others[3] | 0 | 1 | 1 | |
| false | 0 | 1 | 1 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| true | 5254 | 1 | T1 | 24 | T5 | 1 | T8 | 25 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 614 | 1 | T93 | 11 | T35 | 9 | T139 | 4 | ||||
| others[1] | 659 | 1 | T93 | 15 | T35 | 19 | T139 | 6 | ||||
| others[2] | 638 | 1 | T93 | 14 | T35 | 23 | T139 | 5 | ||||
| others[3] | 1040 | 1 | T93 | 25 | T35 | 27 | T139 | 10 | ||||
| false | 22646 | 1 | T1 | 55 | T2 | 11 | T3 | 1 | ||||
| true | 2260 | 1 | T1 | 5 | T5 | 1 | T10 | 29 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |