Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T5,T7

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11298893	13069	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11298893	120604	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11298893	6665566	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11298893	192733	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11298893	13069	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11298893	120604	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11298893	6665566	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11298893	192733	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	13069	0	0
T1	16029	40	0	0
T2	2859	10	0	0
T3	3357	0	0	0
T4	10033	0	0	0
T5	2656	4	0	0
T6	9656	0	0	0
T7	5127	0	0	0
T8	42420	75	0	0
T9	1807	0	0	0
T10	47748	105	0	0
T12	0	4	0	0
T13	0	75	0	0
T14	0	30	0	0
T15	0	8	0	0
T16	0	5	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	120604	0	0
T1	16029	362	0	0
T2	2859	90	0	0
T3	3357	0	0	0
T4	10033	0	0	0
T5	2656	38	0	0
T6	9656	0	0	0
T7	5127	0	0	0
T8	42420	700	0	0
T9	1807	0	0	0
T10	47748	964	0	0
T12	0	38	0	0
T13	0	723	0	0
T14	0	277	0	0
T15	0	72	0	0
T16	0	45	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	6665566	0	0
T1	16029	8089	0	0
T2	2859	2079	0	0
T3	3357	2714	0	0
T4	10033	9392	0	0
T5	2656	1679	0	0
T6	9656	9084	0	0
T7	5127	602	0	0
T8	42420	24965	0	0
T9	1807	1161	0	0
T10	47748	26967	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	192733	0	0
T1	16029	592	0	0
T2	2859	142	0	0
T3	3357	0	0	0
T4	10033	0	0	0
T5	2656	69	0	0
T6	9656	0	0	0
T7	5127	0	0	0
T8	42420	1127	0	0
T9	1807	0	0	0
T10	47748	1542	0	0
T12	0	53	0	0
T13	0	1160	0	0
T14	0	442	0	0
T15	0	116	0	0
T16	0	66	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	13069	0	0
T1	16029	40	0	0
T2	2859	10	0	0
T3	3357	0	0	0
T4	10033	0	0	0
T5	2656	4	0	0
T6	9656	0	0	0
T7	5127	0	0	0
T8	42420	75	0	0
T9	1807	0	0	0
T10	47748	105	0	0
T12	0	4	0	0
T13	0	75	0	0
T14	0	30	0	0
T15	0	8	0	0
T16	0	5	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	120604	0	0
T1	16029	362	0	0
T2	2859	90	0	0
T3	3357	0	0	0
T4	10033	0	0	0
T5	2656	38	0	0
T6	9656	0	0	0
T7	5127	0	0	0
T8	42420	700	0	0
T9	1807	0	0	0
T10	47748	964	0	0
T12	0	38	0	0
T13	0	723	0	0
T14	0	277	0	0
T15	0	72	0	0
T16	0	45	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	6665566	0	0
T1	16029	8089	0	0
T2	2859	2079	0	0
T3	3357	2714	0	0
T4	10033	9392	0	0
T5	2656	1679	0	0
T6	9656	9084	0	0
T7	5127	602	0	0
T8	42420	24965	0	0
T9	1807	1161	0	0
T10	47748	26967	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	192733	0	0
T1	16029	592	0	0
T2	2859	142	0	0
T3	3357	0	0	0
T4	10033	0	0	0
T5	2656	69	0	0
T6	9656	0	0	0
T7	5127	0	0	0
T8	42420	1127	0	0
T9	1807	0	0	0
T10	47748	1542	0	0
T12	0	53	0	0
T13	0	1160	0	0
T14	0	442	0	0
T15	0	116	0	0
T16	0	66	0	0