Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T10
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T10,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T5,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53254973	8601	0	0
CascadeEffAonToRstPorAboveRise_A	53254973	8601	0	0
CascadeEffAonToRstPorIoAboveFall_A	51122942	8601	0	0
CascadeEffAonToRstPorIoAboveRise_A	51122942	8601	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25562171	8601	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25562171	8601	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12780832	8601	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12780832	8601	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25562211	8601	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25562211	8601	0	0
CascadeLcToLcAboveFall_A	53254973	21670	0	0
CascadeLcToLcAboveRise_A	53254973	21670	0	0
CascadeLcToLcAonAboveFall_A	1614505	21670	0	0
CascadeLcToLcAonAboveRise_A	1614505	21670	0	0
CascadeLcToLcShadowedAboveFall_A	53254973	21670	0	0
CascadeLcToLcShadowedAboveRise_A	53254973	21670	0	0
CascadePorToAonAboveFall_A	1614505	6804	0	0
CascadeSysToSysAboveFall_A	53254973	21670	0	0
CascadeSysToSysAboveRise_A	53254973	21670	0	0
ScanRstToAonRise_A	1614505	215	0	0
StablePorToAonRise_A	1614505	8601	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11298893	21670	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11298893	21670	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11298893	21670	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11298893	21670	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12780832	21670	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12780832	21670	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11298893	21670	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11298893	21670	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11298893	21670	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11298893	21670	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	8601	0	0
T1	86935	15	0	0
T2	15341	1	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	2	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	27	0	0
T9	7609	1	0	0
T10	251487	48	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	8601	0	0
T1	86935	15	0	0
T2	15341	1	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	2	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	27	0	0
T9	7609	1	0	0
T10	251487	48	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51122942	8601	0	0
T1	83442	15	0	0
T2	14727	1	0	0
T3	13504	1	0	0
T4	40210	1	0	0
T5	11777	2	0	0
T6	38988	1	0	0
T7	23459	8	0	0
T8	181227	27	0	0
T9	7305	1	0	0
T10	241447	48	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51122942	8601	0	0
T1	83442	15	0	0
T2	14727	1	0	0
T3	13504	1	0	0
T4	40210	1	0	0
T5	11777	2	0	0
T6	38988	1	0	0
T7	23459	8	0	0
T8	181227	27	0	0
T9	7305	1	0	0
T10	241447	48	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562171	8601	0	0
T1	41732	15	0	0
T2	7363	1	0	0
T3	6751	1	0	0
T4	20105	1	0	0
T5	5889	2	0	0
T6	19495	1	0	0
T7	11734	8	0	0
T8	90618	27	0	0
T9	3652	1	0	0
T10	120737	48	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562171	8601	0	0
T1	41732	15	0	0
T2	7363	1	0	0
T3	6751	1	0	0
T4	20105	1	0	0
T5	5889	2	0	0
T6	19495	1	0	0
T7	11734	8	0	0
T8	90618	27	0	0
T9	3652	1	0	0
T10	120737	48	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	8601	0	0
T1	20864	15	0	0
T2	3680	1	0	0
T3	3375	1	0	0
T4	10051	1	0	0
T5	2944	2	0	0
T6	9747	1	0	0
T7	5865	8	0	0
T8	45314	27	0	0
T9	1825	1	0	0
T10	60361	48	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	8601	0	0
T1	20864	15	0	0
T2	3680	1	0	0
T3	3375	1	0	0
T4	10051	1	0	0
T5	2944	2	0	0
T6	9747	1	0	0
T7	5865	8	0	0
T8	45314	27	0	0
T9	1825	1	0	0
T10	60361	48	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562211	8601	0	0
T1	41729	15	0	0
T2	7363	1	0	0
T3	6752	1	0	0
T4	20106	1	0	0
T5	5888	2	0	0
T6	19495	1	0	0
T7	11731	8	0	0
T8	90625	27	0	0
T9	3652	1	0	0
T10	120721	48	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562211	8601	0	0
T1	41729	15	0	0
T2	7363	1	0	0
T3	6752	1	0	0
T4	20106	1	0	0
T5	5888	2	0	0
T6	19495	1	0	0
T7	11731	8	0	0
T8	90625	27	0	0
T9	3652	1	0	0
T10	120721	48	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	21670	0	0
T1	86935	55	0	0
T2	15341	11	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	6	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	102	0	0
T9	7609	1	0	0
T10	251487	153	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	21670	0	0
T1	86935	55	0	0
T2	15341	11	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	6	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	102	0	0
T9	7609	1	0	0
T10	251487	153	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	21670	0	0
T1	2705	55	0	0
T2	460	11	0	0
T3	421	1	0	0
T4	1256	1	0	0
T5	366	6	0	0
T6	1217	1	0	0
T7	734	8	0	0
T8	5679	102	0	0
T9	227	1	0	0
T10	7696	153	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	21670	0	0
T1	2705	55	0	0
T2	460	11	0	0
T3	421	1	0	0
T4	1256	1	0	0
T5	366	6	0	0
T6	1217	1	0	0
T7	734	8	0	0
T8	5679	102	0	0
T9	227	1	0	0
T10	7696	153	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	21670	0	0
T1	86935	55	0	0
T2	15341	11	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	6	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	102	0	0
T9	7609	1	0	0
T10	251487	153	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	21670	0	0
T1	86935	55	0	0
T2	15341	11	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	6	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	102	0	0
T9	7609	1	0	0
T10	251487	153	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	6804	0	0
T1	2705	10	0	0
T2	460	1	0	0
T3	421	1	0	0
T4	1256	1	0	0
T5	366	1	0	0
T6	1217	1	0	0
T7	734	8	0	0
T8	5679	27	0	0
T9	227	1	0	0
T10	7696	19	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	21670	0	0
T1	86935	55	0	0
T2	15341	11	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	6	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	102	0	0
T9	7609	1	0	0
T10	251487	153	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53254973	21670	0	0
T1	86935	55	0	0
T2	15341	11	0	0
T3	14068	1	0	0
T4	41885	1	0	0
T5	12274	6	0	0
T6	40614	1	0	0
T7	24451	8	0	0
T8	188775	102	0	0
T9	7609	1	0	0
T10	251487	153	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	215	0	0
T10	7696	1	0	0
T11	1105	0	0	0
T12	622	0	0	0
T13	3652	0	0	0
T14	0	2	0	0
T17	730	0	0	0
T18	730	0	0	0
T19	734	0	0	0
T20	730	0	0	0
T31	0	4	0	0
T38	0	2	0	0
T50	0	4	0	0
T52	0	1	0	0
T66	238	0	0	0
T88	0	2	0	0
T94	842	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	11	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	8601	0	0
T1	2705	15	0	0
T2	460	1	0	0
T3	421	1	0	0
T4	1256	1	0	0
T5	366	2	0	0
T6	1217	1	0	0
T7	734	8	0	0
T8	5679	27	0	0
T9	227	1	0	0
T10	7696	48	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	21670	0	0
T1	20864	55	0	0
T2	3680	11	0	0
T3	3375	1	0	0
T4	10051	1	0	0
T5	2944	6	0	0
T6	9747	1	0	0
T7	5865	8	0	0
T8	45314	102	0	0
T9	1825	1	0	0
T10	60361	153	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	21670	0	0
T1	20864	55	0	0
T2	3680	11	0	0
T3	3375	1	0	0
T4	10051	1	0	0
T5	2944	6	0	0
T6	9747	1	0	0
T7	5865	8	0	0
T8	45314	102	0	0
T9	1825	1	0	0
T10	60361	153	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11298893	21670	0	0
T1	16029	55	0	0
T2	2859	11	0	0
T3	3357	1	0	0
T4	10033	1	0	0
T5	2656	6	0	0
T6	9656	1	0	0
T7	5127	8	0	0
T8	42420	102	0	0
T9	1807	1	0	0
T10	47748	153	0	0