Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12780832	14002	0	0
gen_assertions[0].RstEnOn_A	12780832	1102	0	0
gen_assertions[0].RstNOff_A	12780832	14002	0	0
gen_assertions[0].RstNOn_A	12780832	1102	0	0
gen_assertions[1].RstEnOff_A	51122942	12743	0	0
gen_assertions[1].RstEnOn_A	51122942	1047	0	0
gen_assertions[1].RstNOff_A	51122942	12743	0	0
gen_assertions[1].RstNOn_A	51122942	1047	0	0
gen_assertions[2].RstEnOff_A	25562171	12812	0	0
gen_assertions[2].RstEnOn_A	25562171	1084	0	0
gen_assertions[2].RstNOff_A	25562171	12812	0	0
gen_assertions[2].RstNOn_A	25562171	1084	0	0
gen_assertions[3].RstEnOff_A	25562211	12841	0	0
gen_assertions[3].RstEnOn_A	25562211	1110	0	0
gen_assertions[3].RstNOff_A	25562211	12841	0	0
gen_assertions[3].RstNOn_A	25562211	1110	0	0
gen_assertions[4].RstEnOff_A	1614505	21485	0	0
gen_assertions[4].RstEnOn_A	1614505	1173	0	0
gen_assertions[4].RstNOff_A	1614505	21485	0	0
gen_assertions[4].RstNOn_A	1614505	1173	0	0
gen_assertions[5].RstEnOff_A	12780832	14250	0	0
gen_assertions[5].RstEnOn_A	12780832	1231	0	0
gen_assertions[5].RstNOff_A	12780832	14250	0	0
gen_assertions[5].RstNOn_A	12780832	1231	0	0
gen_assertions[6].RstEnOff_A	12780832	14328	0	0
gen_assertions[6].RstEnOn_A	12780832	1301	0	0
gen_assertions[6].RstNOff_A	12780832	14328	0	0
gen_assertions[6].RstNOn_A	12780832	1301	0	0
gen_assertions[7].RstEnOff_A	12780832	14365	0	0
gen_assertions[7].RstEnOn_A	12780832	1342	0	0
gen_assertions[7].RstNOff_A	12780832	14365	0	0
gen_assertions[7].RstNOn_A	12780832	1342	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14002	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	3	0	0
T4	10051	6	0	0
T5	2944	4	0	0
T6	9747	3	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	118	0	0
T11	0	7	0	0
T12	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1102	0	0
T2	3680	1	0	0
T3	3375	3	0	0
T4	10051	6	0	0
T5	2944	0	0	0
T6	9747	3	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	13	0	0
T11	0	7	0	0
T16	0	1	0	0
T17	5833	0	0	0
T32	0	3	0	0
T91	0	1	0	0
T94	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14002	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	3	0	0
T4	10051	6	0	0
T5	2944	4	0	0
T6	9747	3	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	118	0	0
T11	0	7	0	0
T12	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1102	0	0
T2	3680	1	0	0
T3	3375	3	0	0
T4	10051	6	0	0
T5	2944	0	0	0
T6	9747	3	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	13	0	0
T11	0	7	0	0
T16	0	1	0	0
T17	5833	0	0	0
T32	0	3	0	0
T91	0	1	0	0
T94	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51122942	12743	0	0
T1	83442	35	0	0
T2	14727	9	0	0
T3	13504	6	0	0
T4	40210	5	0	0
T5	11777	4	0	0
T6	38988	4	0	0
T7	23459	0	0	0
T8	181227	68	0	0
T9	7305	0	0	0
T10	241447	108	0	0
T11	0	8	0	0
T12	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51122942	1047	0	0
T3	13504	6	0	0
T4	40210	5	0	0
T5	11777	0	0	0
T6	38988	4	0	0
T7	23459	0	0	0
T8	181227	0	0	0
T9	7305	0	0	0
T10	241447	17	0	0
T11	0	8	0	0
T17	23332	0	0	0
T32	0	4	0	0
T33	0	4	0	0
T36	0	1	0	0
T37	0	6	0	0
T66	7667	0	0	0
T94	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51122942	12743	0	0
T1	83442	35	0	0
T2	14727	9	0	0
T3	13504	6	0	0
T4	40210	5	0	0
T5	11777	4	0	0
T6	38988	4	0	0
T7	23459	0	0	0
T8	181227	68	0	0
T9	7305	0	0	0
T10	241447	108	0	0
T11	0	8	0	0
T12	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51122942	1047	0	0
T3	13504	6	0	0
T4	40210	5	0	0
T5	11777	0	0	0
T6	38988	4	0	0
T7	23459	0	0	0
T8	181227	0	0	0
T9	7305	0	0	0
T10	241447	17	0	0
T11	0	8	0	0
T17	23332	0	0	0
T32	0	4	0	0
T33	0	4	0	0
T36	0	1	0	0
T37	0	6	0	0
T66	7667	0	0	0
T94	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562171	12812	0	0
T1	41732	35	0	0
T2	7363	9	0	0
T3	6751	4	0	0
T4	20105	7	0	0
T5	5889	4	0	0
T6	19495	6	0	0
T7	11734	0	0	0
T8	90618	68	0	0
T9	3652	0	0	0
T10	120737	108	0	0
T11	0	9	0	0
T12	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562171	1084	0	0
T3	6751	4	0	0
T4	20105	7	0	0
T5	5889	0	0	0
T6	19495	6	0	0
T7	11734	0	0	0
T8	90618	0	0	0
T9	3652	0	0	0
T10	120737	16	0	0
T11	0	9	0	0
T17	11671	0	0	0
T32	0	4	0	0
T33	0	6	0	0
T36	0	3	0	0
T66	3832	0	0	0
T90	0	1	0	0
T94	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562171	12812	0	0
T1	41732	35	0	0
T2	7363	9	0	0
T3	6751	4	0	0
T4	20105	7	0	0
T5	5889	4	0	0
T6	19495	6	0	0
T7	11734	0	0	0
T8	90618	68	0	0
T9	3652	0	0	0
T10	120737	108	0	0
T11	0	9	0	0
T12	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562171	1084	0	0
T3	6751	4	0	0
T4	20105	7	0	0
T5	5889	0	0	0
T6	19495	6	0	0
T7	11734	0	0	0
T8	90618	0	0	0
T9	3652	0	0	0
T10	120737	16	0	0
T11	0	9	0	0
T17	11671	0	0	0
T32	0	4	0	0
T33	0	6	0	0
T36	0	3	0	0
T66	3832	0	0	0
T90	0	1	0	0
T94	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562211	12841	0	0
T1	41729	35	0	0
T2	7363	9	0	0
T3	6752	7	0	0
T4	20106	7	0	0
T5	5888	4	0	0
T6	19495	6	0	0
T7	11731	0	0	0
T8	90625	68	0	0
T9	3652	0	0	0
T10	120721	107	0	0
T11	0	8	0	0
T12	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562211	1110	0	0
T3	6752	7	0	0
T4	20106	7	0	0
T5	5888	0	0	0
T6	19495	6	0	0
T7	11731	0	0	0
T8	90625	0	0	0
T9	3652	0	0	0
T10	120721	16	0	0
T11	0	8	0	0
T12	0	1	0	0
T17	11665	0	0	0
T32	0	5	0	0
T33	0	7	0	0
T36	0	4	0	0
T66	3833	0	0	0
T94	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562211	12841	0	0
T1	41729	35	0	0
T2	7363	9	0	0
T3	6752	7	0	0
T4	20106	7	0	0
T5	5888	4	0	0
T6	19495	6	0	0
T7	11731	0	0	0
T8	90625	68	0	0
T9	3652	0	0	0
T10	120721	107	0	0
T11	0	8	0	0
T12	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25562211	1110	0	0
T3	6752	7	0	0
T4	20106	7	0	0
T5	5888	0	0	0
T6	19495	6	0	0
T7	11731	0	0	0
T8	90625	0	0	0
T9	3652	0	0	0
T10	120721	16	0	0
T11	0	8	0	0
T12	0	1	0	0
T17	11665	0	0	0
T32	0	5	0	0
T33	0	7	0	0
T36	0	4	0	0
T66	3833	0	0	0
T94	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	21485	0	0
T1	2705	54	0	0
T2	460	11	0	0
T3	421	10	0	0
T4	1256	8	0	0
T5	366	6	0	0
T6	1217	7	0	0
T7	734	3	0	0
T8	5679	92	0	0
T9	227	1	0	0
T10	7696	166	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	1173	0	0
T3	421	9	0	0
T4	1256	7	0	0
T5	366	0	0	0
T6	1217	6	0	0
T7	734	0	0	0
T8	5679	0	0	0
T9	227	0	0	0
T10	7696	17	0	0
T11	0	9	0	0
T17	730	0	0	0
T32	0	4	0	0
T33	0	8	0	0
T36	0	5	0	0
T66	238	0	0	0
T90	0	1	0	0
T94	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	21485	0	0
T1	2705	54	0	0
T2	460	11	0	0
T3	421	10	0	0
T4	1256	8	0	0
T5	366	6	0	0
T6	1217	7	0	0
T7	734	3	0	0
T8	5679	92	0	0
T9	227	1	0	0
T10	7696	166	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614505	1173	0	0
T3	421	9	0	0
T4	1256	7	0	0
T5	366	0	0	0
T6	1217	6	0	0
T7	734	0	0	0
T8	5679	0	0	0
T9	227	0	0	0
T10	7696	17	0	0
T11	0	9	0	0
T17	730	0	0	0
T32	0	4	0	0
T33	0	8	0	0
T36	0	5	0	0
T66	238	0	0	0
T90	0	1	0	0
T94	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14250	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	9	0	0
T4	10051	8	0	0
T5	2944	4	0	0
T6	9747	7	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	122	0	0
T11	0	10	0	0
T12	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1231	0	0
T3	3375	9	0	0
T4	10051	8	0	0
T5	2944	0	0	0
T6	9747	7	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	17	0	0
T11	0	10	0	0
T17	5833	0	0	0
T32	0	6	0	0
T33	0	8	0	0
T36	0	6	0	0
T66	1916	0	0	0
T91	0	1	0	0
T94	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14250	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	9	0	0
T4	10051	8	0	0
T5	2944	4	0	0
T6	9747	7	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	122	0	0
T11	0	10	0	0
T12	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1231	0	0
T3	3375	9	0	0
T4	10051	8	0	0
T5	2944	0	0	0
T6	9747	7	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	17	0	0
T11	0	10	0	0
T17	5833	0	0	0
T32	0	6	0	0
T33	0	8	0	0
T36	0	6	0	0
T66	1916	0	0	0
T91	0	1	0	0
T94	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14328	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	11	0	0
T4	10051	12	0	0
T5	2944	4	0	0
T6	9747	9	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	121	0	0
T11	0	14	0	0
T12	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1301	0	0
T3	3375	11	0	0
T4	10051	12	0	0
T5	2944	0	0	0
T6	9747	9	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	16	0	0
T11	0	14	0	0
T17	5833	0	0	0
T32	0	7	0	0
T33	0	10	0	0
T36	0	6	0	0
T37	0	10	0	0
T66	1916	0	0	0
T94	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14328	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	11	0	0
T4	10051	12	0	0
T5	2944	4	0	0
T6	9747	9	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	121	0	0
T11	0	14	0	0
T12	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1301	0	0
T3	3375	11	0	0
T4	10051	12	0	0
T5	2944	0	0	0
T6	9747	9	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	16	0	0
T11	0	14	0	0
T17	5833	0	0	0
T32	0	7	0	0
T33	0	10	0	0
T36	0	6	0	0
T37	0	10	0	0
T66	1916	0	0	0
T94	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14365	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	10	0	0
T4	10051	10	0	0
T5	2944	4	0	0
T6	9747	10	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	119	0	0
T11	0	14	0	0
T12	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1342	0	0
T3	3375	10	0	0
T4	10051	10	0	0
T5	2944	0	0	0
T6	9747	10	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	14	0	0
T11	0	14	0	0
T17	5833	0	0	0
T32	0	8	0	0
T33	0	11	0	0
T36	0	8	0	0
T66	1916	0	0	0
T90	0	1	0	0
T94	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	14365	0	0
T1	20864	40	0	0
T2	3680	10	0	0
T3	3375	10	0	0
T4	10051	10	0	0
T5	2944	4	0	0
T6	9747	10	0	0
T7	5865	0	0	0
T8	45314	75	0	0
T9	1825	0	0	0
T10	60361	119	0	0
T11	0	14	0	0
T12	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12780832	1342	0	0
T3	3375	10	0	0
T4	10051	10	0	0
T5	2944	0	0	0
T6	9747	10	0	0
T7	5865	0	0	0
T8	45314	0	0	0
T9	1825	0	0	0
T10	60361	14	0	0
T11	0	14	0	0
T17	5833	0	0	0
T32	0	8	0	0
T33	0	11	0	0
T36	0	8	0	0
T66	1916	0	0	0
T90	0	1	0	0
T94	0	8	0	0