Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12122235	9083	0	0
alert_regwen_rd_A	12122235	5479	0	0
cpu_regwen_rd_A	12122235	5761	0	0
sw_rst_ctrl_n_0_rd_A	12122235	9690	0	0
sw_rst_ctrl_n_1_rd_A	12122235	10024	0	0
sw_rst_ctrl_n_2_rd_A	12122235	9969	0	0
sw_rst_ctrl_n_3_rd_A	12122235	10242	0	0
sw_rst_ctrl_n_4_rd_A	12122235	9826	0	0
sw_rst_ctrl_n_5_rd_A	12122235	10215	0	0
sw_rst_ctrl_n_6_rd_A	12122235	9971	0	0
sw_rst_ctrl_n_7_rd_A	12122235	9937	0	0
sw_rst_regwen_0_rd_A	12122235	5799	0	0
sw_rst_regwen_1_rd_A	12122235	5888	0	0
sw_rst_regwen_2_rd_A	12122235	5888	0	0
sw_rst_regwen_3_rd_A	12122235	5680	0	0
sw_rst_regwen_4_rd_A	12122235	6000	0	0
sw_rst_regwen_5_rd_A	12122235	5751	0	0
sw_rst_regwen_6_rd_A	12122235	5941	0	0
sw_rst_regwen_7_rd_A	12122235	5875	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	9083	0	0
T73	21169	1	0	0
T74	5810	182	0	0
T75	10342	459	0	0
T76	3998	13	0	0
T77	19556	3	0	0
T97	4305	22	0	0
T98	17164	3	0	0
T99	8906	374	0	0
T103	19060	5	0	0
T122	10424	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5479	0	0
T31	230744	344	0	0
T32	2846	0	0	0
T33	10788	0	0	0
T34	26013	0	0	0
T35	3566	0	0	0
T36	5949	0	0	0
T37	7677	0	0	0
T38	15150	0	0	0
T39	1851	0	0	0
T88	0	59	0	0
T105	0	24	0	0
T106	0	507	0	0
T111	1846	0	0	0
T113	0	361	0	0
T129	0	277	0	0
T130	0	288	0	0
T131	0	25	0	0
T132	0	119	0	0
T133	0	306	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5761	0	0
T31	230744	394	0	0
T32	2846	0	0	0
T33	10788	0	0	0
T34	26013	0	0	0
T35	3566	0	0	0
T36	5949	0	0	0
T37	7677	0	0	0
T38	15150	0	0	0
T39	1851	0	0	0
T88	0	66	0	0
T105	0	28	0	0
T106	0	522	0	0
T111	1846	0	0	0
T113	0	338	0	0
T129	0	273	0	0
T130	0	305	0	0
T131	0	52	0	0
T132	0	94	0	0
T133	0	365	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	9690	0	0
T4	10033	78	0	0
T5	2656	0	0	0
T6	9656	188	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	18	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	336	0	0
T33	0	146	0	0
T66	1849	0	0	0
T84	0	75	0	0
T86	0	70	0	0
T88	0	50	0	0
T105	0	37	0	0
T134	0	10	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	10024	0	0
T4	10033	86	0	0
T5	2656	0	0	0
T6	9656	139	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	32	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	424	0	0
T33	0	173	0	0
T66	1849	0	0	0
T84	0	73	0	0
T86	0	70	0	0
T88	0	53	0	0
T105	0	30	0	0
T134	0	9	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	9969	0	0
T4	10033	103	0	0
T5	2656	0	0	0
T6	9656	133	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	17	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	373	0	0
T33	0	153	0	0
T66	1849	0	0	0
T84	0	89	0	0
T86	0	69	0	0
T88	0	65	0	0
T105	0	33	0	0
T134	0	15	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	10242	0	0
T4	10033	79	0	0
T5	2656	0	0	0
T6	9656	128	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	8	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	341	0	0
T33	0	174	0	0
T66	1849	0	0	0
T84	0	66	0	0
T86	0	64	0	0
T88	0	54	0	0
T105	0	35	0	0
T134	0	14	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	9826	0	0
T4	10033	112	0	0
T5	2656	0	0	0
T6	9656	126	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	8	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	402	0	0
T33	0	130	0	0
T66	1849	0	0	0
T84	0	125	0	0
T86	0	76	0	0
T88	0	57	0	0
T105	0	6	0	0
T134	0	9	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	10215	0	0
T4	10033	120	0	0
T5	2656	0	0	0
T6	9656	131	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	12	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	393	0	0
T33	0	177	0	0
T66	1849	0	0	0
T84	0	104	0	0
T86	0	73	0	0
T88	0	64	0	0
T105	0	25	0	0
T134	0	17	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	9971	0	0
T4	10033	125	0	0
T5	2656	0	0	0
T6	9656	121	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	19	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	401	0	0
T33	0	127	0	0
T66	1849	0	0	0
T84	0	87	0	0
T86	0	81	0	0
T88	0	69	0	0
T105	0	33	0	0
T134	0	17	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	9937	0	0
T4	10033	98	0	0
T5	2656	0	0	0
T6	9656	132	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T15	0	16	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	475	0	0
T33	0	164	0	0
T66	1849	0	0	0
T84	0	74	0	0
T86	0	57	0	0
T88	0	48	0	0
T105	0	35	0	0
T134	0	22	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5799	0	0
T4	10033	12	0	0
T5	2656	0	0	0
T6	9656	39	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	363	0	0
T33	0	40	0	0
T66	1849	0	0	0
T84	0	24	0	0
T88	0	65	0	0
T105	0	18	0	0
T106	0	540	0	0
T113	0	365	0	0
T134	0	11	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5888	0	0
T4	10033	13	0	0
T5	2656	0	0	0
T6	9656	19	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	393	0	0
T33	0	30	0	0
T66	1849	0	0	0
T84	0	32	0	0
T88	0	62	0	0
T105	0	48	0	0
T106	0	524	0	0
T134	0	8	0	0
T135	0	1	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5888	0	0
T4	10033	20	0	0
T5	2656	0	0	0
T6	9656	32	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	373	0	0
T33	0	25	0	0
T66	1849	0	0	0
T84	0	31	0	0
T88	0	58	0	0
T105	0	21	0	0
T106	0	488	0	0
T134	0	9	0	0
T135	0	12	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5680	0	0
T4	10033	14	0	0
T5	2656	0	0	0
T6	9656	41	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	375	0	0
T33	0	37	0	0
T66	1849	0	0	0
T84	0	25	0	0
T88	0	60	0	0
T105	0	23	0	0
T106	0	489	0	0
T134	0	6	0	0
T135	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	6000	0	0
T4	10033	42	0	0
T5	2656	0	0	0
T6	9656	25	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	395	0	0
T33	0	24	0	0
T66	1849	0	0	0
T84	0	26	0	0
T88	0	64	0	0
T105	0	36	0	0
T106	0	483	0	0
T134	0	4	0	0
T135	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5751	0	0
T4	10033	10	0	0
T5	2656	0	0	0
T6	9656	31	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	379	0	0
T33	0	32	0	0
T66	1849	0	0	0
T84	0	40	0	0
T88	0	44	0	0
T105	0	29	0	0
T106	0	541	0	0
T134	0	8	0	0
T135	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5941	0	0
T4	10033	7	0	0
T5	2656	0	0	0
T6	9656	24	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	409	0	0
T33	0	23	0	0
T66	1849	0	0	0
T84	0	25	0	0
T88	0	60	0	0
T105	0	31	0	0
T106	0	489	0	0
T134	0	7	0	0
T135	0	5	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122235	5875	0	0
T4	10033	18	0	0
T5	2656	0	0	0
T6	9656	33	0	0
T7	5127	0	0	0
T8	42420	0	0	0
T9	1807	0	0	0
T10	47748	0	0	0
T17	5288	0	0	0
T18	5476	0	0	0
T31	0	363	0	0
T33	0	21	0	0
T66	1849	0	0	0
T84	0	20	0	0
T88	0	58	0	0
T105	0	32	0	0
T106	0	559	0	0
T134	0	3	0	0
T135	0	1	0	0