Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	600650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

361039

1

T3

1105

T4

1089

T5

442

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	510688	1			T3	1500		T4	1500		T5	587
values[0x0]	225541	1			T3	868		T4	836		T5	287
values[0x1]	225460	1			T3	832		T4	864		T5	254

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	504346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

457343

1

T3

1438

T4

1398

T5

538

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3258	1			T3	18		T4	11		T7	69
valid_sources[0x01]	3874	1			T3	31		T4	7		T6	3
valid_sources[0x02]	3045	1			T3	17		T4	8		T6	2
valid_sources[0x03]	3458	1			T3	15		T4	17		T6	4
valid_sources[0x04]	4459	1			T3	14		T4	13		T7	72
valid_sources[0x05]	3438	1			T3	25		T4	13		T7	53
valid_sources[0x06]	2979	1			T3	6		T4	15		T7	61
valid_sources[0x07]	3623	1			T4	7		T6	1		T7	70
valid_sources[0x08]	3110	1			T4	19		T6	3		T7	89
valid_sources[0x09]	2923	1			T4	14		T7	82		T10	12
valid_sources[0x0a]	7069	1			T3	9		T4	13		T6	2
valid_sources[0x0b]	3352	1			T4	8		T7	77		T10	11
valid_sources[0x0c]	3232	1			T3	5		T4	12		T6	1
valid_sources[0x0d]	3816	1			T4	10		T6	2		T7	79
valid_sources[0x0e]	3178	1			T3	15		T4	15		T6	1
valid_sources[0x0f]	2990	1			T3	14		T4	10		T7	79
valid_sources[0x10]	6520	1			T3	15		T4	16		T7	61
valid_sources[0x11]	3409	1			T3	13		T4	13		T6	1
valid_sources[0x12]	3770	1			T3	13		T4	13		T7	70
valid_sources[0x13]	3372	1			T3	14		T4	13		T7	71
valid_sources[0x14]	3035	1			T4	9		T6	1		T7	89
valid_sources[0x15]	4008	1			T3	9		T4	9		T7	58
valid_sources[0x16]	3276	1			T4	13		T7	91		T10	13
valid_sources[0x17]	3053	1			T4	15		T7	71		T10	10
valid_sources[0x18]	2916	1			T3	8		T4	9		T7	53
valid_sources[0x19]	3070	1			T3	6		T4	15		T7	59
valid_sources[0x1a]	6590	1			T3	5		T4	12		T6	1
valid_sources[0x1b]	3209	1			T3	16		T4	12		T6	1
valid_sources[0x1c]	4146	1			T3	32		T4	17		T7	84
valid_sources[0x1d]	3060	1			T3	13		T4	14		T7	63
valid_sources[0x1e]	3574	1			T3	4		T4	6		T7	63
valid_sources[0x1f]	3320	1			T3	9		T4	11		T7	53
valid_sources[0x20]	3434	1			T3	12		T4	14		T6	1
valid_sources[0x21]	3605	1			T3	36		T4	15		T7	77
valid_sources[0x22]	4204	1			T4	14		T7	67		T10	16
valid_sources[0x23]	3854	1			T3	4		T4	5		T6	2
valid_sources[0x24]	4233	1			T3	21		T4	14		T6	1
valid_sources[0x25]	3223	1			T3	23		T4	20		T7	62
valid_sources[0x26]	3435	1			T3	6		T4	15		T7	60
valid_sources[0x27]	3309	1			T3	17		T4	12		T7	72
valid_sources[0x28]	3450	1			T3	33		T4	9		T7	73
valid_sources[0x29]	3538	1			T3	35		T4	17		T6	1
valid_sources[0x2a]	3745	1			T3	15		T4	12		T6	2
valid_sources[0x2b]	3618	1			T3	12		T4	11		T7	75
valid_sources[0x2c]	3535	1			T3	18		T4	9		T6	1
valid_sources[0x2d]	3270	1			T3	64		T4	13		T7	80
valid_sources[0x2e]	3276	1			T4	9		T6	2		T7	63
valid_sources[0x2f]	4386	1			T4	18		T6	1		T7	80
valid_sources[0x30]	2908	1			T3	20		T4	15		T6	1
valid_sources[0x31]	9569	1			T3	3		T4	15		T7	55
valid_sources[0x32]	3555	1			T3	11		T4	12		T7	40
valid_sources[0x33]	3788	1			T3	8		T4	12		T7	71
valid_sources[0x34]	4374	1			T3	33		T4	8		T6	1
valid_sources[0x35]	3411	1			T3	7		T4	11		T7	83
valid_sources[0x36]	3762	1			T3	17		T4	7		T6	1
valid_sources[0x37]	3496	1			T4	16		T6	1		T7	72
valid_sources[0x38]	3803	1			T3	11		T4	12		T7	93
valid_sources[0x39]	3145	1			T3	15		T4	10		T6	2
valid_sources[0x3a]	3855	1			T3	2		T4	10		T6	1
valid_sources[0x3b]	3582	1			T3	25		T4	18		T6	1
valid_sources[0x3c]	4294	1			T3	15		T4	7		T6	1
valid_sources[0x3d]	3093	1			T3	10		T4	14		T6	3
valid_sources[0x3e]	3390	1			T3	25		T4	17		T6	1
valid_sources[0x3f]	3453	1			T4	7		T7	81		T9	4
valid_sources[0x40]	3035	1			T4	10		T6	1		T7	41
valid_sources[0x41]	3191	1			T3	4		T4	16		T6	1
valid_sources[0x42]	3099	1			T3	1		T4	12		T7	68
valid_sources[0x43]	3313	1			T3	18		T4	9		T6	1
valid_sources[0x44]	3667	1			T3	3		T4	13		T6	2
valid_sources[0x45]	3521	1			T3	45		T4	10		T7	82
valid_sources[0x46]	3109	1			T3	8		T4	12		T7	45
valid_sources[0x47]	2977	1			T3	21		T4	15		T7	61
valid_sources[0x48]	4426	1			T3	27		T4	11		T6	1
valid_sources[0x49]	3234	1			T4	15		T7	68		T10	6
valid_sources[0x4a]	3417	1			T3	14		T4	10		T7	69
valid_sources[0x4b]	3949	1			T3	12		T4	11		T6	5
valid_sources[0x4c]	2971	1			T3	21		T4	19		T6	3
valid_sources[0x4d]	3222	1			T3	8		T4	12		T7	80
valid_sources[0x4e]	2835	1			T3	2		T4	10		T7	64
valid_sources[0x4f]	6825	1			T3	18		T4	11		T6	1
valid_sources[0x50]	5194	1			T3	12		T4	9		T5	1128
valid_sources[0x51]	3182	1			T3	22		T4	6		T6	1
valid_sources[0x52]	3593	1			T3	39		T4	23		T6	3
valid_sources[0x53]	3546	1			T3	23		T4	14		T7	64
valid_sources[0x54]	4974	1			T3	9		T4	16		T7	84
valid_sources[0x55]	3039	1			T3	3		T4	12		T7	88
valid_sources[0x56]	3779	1			T3	17		T4	14		T7	66
valid_sources[0x57]	3797	1			T3	2		T4	16		T7	100
valid_sources[0x58]	3625	1			T3	35		T4	9		T7	68
valid_sources[0x59]	4192	1			T3	13		T4	8		T7	86
valid_sources[0x5a]	5499	1			T3	17		T4	6		T6	1
valid_sources[0x5b]	3129	1			T3	10		T4	12		T7	73
valid_sources[0x5c]	3770	1			T4	17		T6	1		T7	71
valid_sources[0x5d]	3264	1			T3	5		T4	13		T7	60
valid_sources[0x5e]	3423	1			T3	8		T4	9		T6	2
valid_sources[0x5f]	4030	1			T3	10		T4	10		T7	57
valid_sources[0x60]	3435	1			T3	9		T4	18		T7	73
valid_sources[0x61]	3278	1			T3	20		T4	10		T6	2
valid_sources[0x62]	3052	1			T3	3		T4	17		T7	68
valid_sources[0x63]	3242	1			T3	2		T4	12		T6	2
valid_sources[0x64]	3219	1			T3	25		T4	14		T6	2
valid_sources[0x65]	3770	1			T4	14		T7	67		T10	11
valid_sources[0x66]	3231	1			T3	6		T4	16		T7	77
valid_sources[0x67]	3265	1			T3	17		T4	12		T7	78
valid_sources[0x68]	3467	1			T3	10		T4	11		T6	1
valid_sources[0x69]	7358	1			T4	7		T7	67		T10	10
valid_sources[0x6a]	3364	1			T3	17		T4	8		T6	1
valid_sources[0x6b]	3426	1			T3	34		T4	12		T6	2
valid_sources[0x6c]	3405	1			T4	12		T6	1		T7	68
valid_sources[0x6d]	3800	1			T3	3		T4	9		T7	89
valid_sources[0x6e]	3265	1			T3	11		T4	12		T7	82
valid_sources[0x6f]	3099	1			T3	9		T4	5		T7	67
valid_sources[0x70]	3145	1			T4	19		T7	56		T10	15
valid_sources[0x71]	3592	1			T3	3		T4	14		T6	1
valid_sources[0x72]	4178	1			T3	3		T4	13		T6	1
valid_sources[0x73]	3463	1			T4	18		T7	74		T9	8
valid_sources[0x74]	3864	1			T3	12		T4	14		T7	89
valid_sources[0x75]	3232	1			T3	14		T4	8		T6	1
valid_sources[0x76]	3724	1			T3	8		T4	12		T6	1
valid_sources[0x77]	3295	1			T3	10		T4	16		T7	59
valid_sources[0x78]	4761	1			T3	25		T4	25		T6	1
valid_sources[0x79]	2983	1			T3	4		T4	13		T6	1
valid_sources[0x7a]	4896	1			T3	5		T4	8		T6	1
valid_sources[0x7b]	3104	1			T3	5		T4	16		T6	1
valid_sources[0x7c]	3513	1			T3	2		T4	13		T7	66
valid_sources[0x7d]	2769	1			T4	6		T6	2		T7	66
valid_sources[0x7e]	4492	1			T3	1		T4	9		T6	1
valid_sources[0x7f]	3797	1			T3	5		T4	9		T6	1
valid_sources[0x80]	3938	1			T3	34		T4	8		T7	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

239584

1

T3

668

T4

696

T5

283

values[0x0]

all_enables

biggest_size

79241

1

T3

293

T4

276

T5

112

values[0x1]

all_enables

biggest_size

42214

1

T3

144

T4

117

T5

47