Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Covered	T6,T7,T12
1	0	Covered	T7,T9,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51953835	8901	0	0
CascadeEffAonToRstPorAboveRise_A	51953835	8901	0	0
CascadeEffAonToRstPorIoAboveFall_A	49875289	8901	0	0
CascadeEffAonToRstPorIoAboveRise_A	49875289	8901	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24938140	8901	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24938140	8901	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12468774	8901	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12468774	8901	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24938221	8901	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24938221	8901	0	0
CascadeLcToLcAboveFall_A	51953835	21772	0	0
CascadeLcToLcAboveRise_A	51953835	21772	0	0
CascadeLcToLcAonAboveFall_A	1574662	21772	0	0
CascadeLcToLcAonAboveRise_A	1574662	21772	0	0
CascadeLcToLcShadowedAboveFall_A	51953835	21772	0	0
CascadeLcToLcShadowedAboveRise_A	51953835	21772	0	0
CascadePorToAonAboveFall_A	1574662	7171	0	0
CascadeSysToSysAboveFall_A	51953835	21772	0	0
CascadeSysToSysAboveRise_A	51953835	21772	0	0
ScanRstToAonRise_A	1574662	216	0	0
StablePorToAonRise_A	1574662	8901	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10971852	21772	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10971852	21772	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10971852	21772	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10971852	21772	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12468774	21772	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12468774	21772	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10971852	21772	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10971852	21772	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10971852	21772	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10971852	21772	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	8901	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	27	0	0
T4	188718	27	0	0
T5	14802	1	0	0
T6	14837	2	0	0
T7	123118	118	0	0
T8	24327	8	0	0
T9	25488	2	0	0
T10	188843	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	8901	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	27	0	0
T4	188718	27	0	0
T5	14802	1	0	0
T6	14837	2	0	0
T7	123118	118	0	0
T8	24327	8	0	0
T9	25488	2	0	0
T10	188843	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49875289	8901	0	0
T1	23317	8	0	0
T2	23249	8	0	0
T3	225743	27	0	0
T4	181157	27	0	0
T5	14209	1	0	0
T6	14238	2	0	0
T7	118188	118	0	0
T8	23351	8	0	0
T9	24469	2	0	0
T10	181295	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49875289	8901	0	0
T1	23317	8	0	0
T2	23249	8	0	0
T3	225743	27	0	0
T4	181157	27	0	0
T5	14209	1	0	0
T6	14238	2	0	0
T7	118188	118	0	0
T8	23351	8	0	0
T9	24469	2	0	0
T10	181295	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938140	8901	0	0
T1	11659	8	0	0
T2	11628	8	0	0
T3	112869	27	0	0
T4	90583	27	0	0
T5	7105	1	0	0
T6	7120	2	0	0
T7	590941	118	0	0
T8	11675	8	0	0
T9	12236	2	0	0
T10	90655	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938140	8901	0	0
T1	11659	8	0	0
T2	11628	8	0	0
T3	112869	27	0	0
T4	90583	27	0	0
T5	7105	1	0	0
T6	7120	2	0	0
T7	590941	118	0	0
T8	11675	8	0	0
T9	12236	2	0	0
T10	90655	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	8901	0	0
T1	5831	8	0	0
T2	5812	8	0	0
T3	56447	27	0	0
T4	45297	27	0	0
T5	3551	1	0	0
T6	3559	2	0	0
T7	295484	118	0	0
T8	5835	8	0	0
T9	6117	2	0	0
T10	45326	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	8901	0	0
T1	5831	8	0	0
T2	5812	8	0	0
T3	56447	27	0	0
T4	45297	27	0	0
T5	3551	1	0	0
T6	3559	2	0	0
T7	295484	118	0	0
T8	5835	8	0	0
T9	6117	2	0	0
T10	45326	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938221	8901	0	0
T1	11658	8	0	0
T2	11633	8	0	0
T3	112877	27	0	0
T4	90579	27	0	0
T5	7105	1	0	0
T6	7121	2	0	0
T7	590974	118	0	0
T8	11675	8	0	0
T9	12235	2	0	0
T10	90648	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938221	8901	0	0
T1	11658	8	0	0
T2	11633	8	0	0
T3	112877	27	0	0
T4	90579	27	0	0
T5	7105	1	0	0
T6	7121	2	0	0
T7	590974	118	0	0
T8	11675	8	0	0
T9	12235	2	0	0
T10	90648	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	21772	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	102	0	0
T4	188718	102	0	0
T5	14802	1	0	0
T6	14837	6	0	0
T7	123118	377	0	0
T8	24327	8	0	0
T9	25488	6	0	0
T10	188843	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	21772	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	102	0	0
T4	188718	102	0	0
T5	14802	1	0	0
T6	14837	6	0	0
T7	123118	377	0	0
T8	24327	8	0	0
T9	25488	6	0	0
T10	188843	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	21772	0	0
T1	731	8	0	0
T2	728	8	0	0
T3	7070	102	0	0
T4	5675	102	0	0
T5	442	1	0	0
T6	444	6	0	0
T7	37366	377	0	0
T8	731	8	0	0
T9	763	6	0	0
T10	5681	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	21772	0	0
T1	731	8	0	0
T2	728	8	0	0
T3	7070	102	0	0
T4	5675	102	0	0
T5	442	1	0	0
T6	444	6	0	0
T7	37366	377	0	0
T8	731	8	0	0
T9	763	6	0	0
T10	5681	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	21772	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	102	0	0
T4	188718	102	0	0
T5	14802	1	0	0
T6	14837	6	0	0
T7	123118	377	0	0
T8	24327	8	0	0
T9	25488	6	0	0
T10	188843	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	21772	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	102	0	0
T4	188718	102	0	0
T5	14802	1	0	0
T6	14837	6	0	0
T7	123118	377	0	0
T8	24327	8	0	0
T9	25488	6	0	0
T10	188843	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	7171	0	0
T1	731	8	0	0
T2	728	8	0	0
T3	7070	27	0	0
T4	5675	27	0	0
T5	442	1	0	0
T6	444	1	0	0
T7	37366	59	0	0
T8	731	8	0	0
T9	763	1	0	0
T10	5681	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	21772	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	102	0	0
T4	188718	102	0	0
T5	14802	1	0	0
T6	14837	6	0	0
T7	123118	377	0	0
T8	24327	8	0	0
T9	25488	6	0	0
T10	188843	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51953835	21772	0	0
T1	24298	8	0	0
T2	24219	8	0	0
T3	235155	102	0	0
T4	188718	102	0	0
T5	14802	1	0	0
T6	14837	6	0	0
T7	123118	377	0	0
T8	24327	8	0	0
T9	25488	6	0	0
T10	188843	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	216	0	0
T7	37366	2	0	0
T8	731	0	0	0
T9	763	0	0	0
T10	5681	0	0	0
T11	342	0	0	0
T12	3920	0	0	0
T13	499	0	0	0
T14	590	1	0	0
T26	0	1	0	0
T27	0	4	0	0
T31	0	1	0	0
T45	51148	0	0	0
T71	731	0	0	0
T74	0	2	0	0
T75	0	1	0	0
T80	0	4	0	0
T90	0	3	0	0
T92	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	8901	0	0
T1	731	8	0	0
T2	728	8	0	0
T3	7070	27	0	0
T4	5675	27	0	0
T5	442	1	0	0
T6	444	2	0	0
T7	37366	118	0	0
T8	731	8	0	0
T9	763	2	0	0
T10	5681	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	21772	0	0
T1	5831	8	0	0
T2	5812	8	0	0
T3	56447	102	0	0
T4	45297	102	0	0
T5	3551	1	0	0
T6	3559	6	0	0
T7	295484	377	0	0
T8	5835	8	0	0
T9	6117	6	0	0
T10	45326	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	21772	0	0
T1	5831	8	0	0
T2	5812	8	0	0
T3	56447	102	0	0
T4	45297	102	0	0
T5	3551	1	0	0
T6	3559	6	0	0
T7	295484	377	0	0
T8	5835	8	0	0
T9	6117	6	0	0
T10	45326	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10971852	21772	0	0
T1	5092	8	0	0
T2	5076	8	0	0
T3	53199	102	0	0
T4	42192	102	0	0
T5	3461	1	0	0
T6	3367	6	0	0
T7	264724	377	0	0
T8	5099	8	0	0
T9	5826	6	0	0
T10	42163	102	0	0