Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T51
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12468774	13788	0	0
gen_assertions[0].RstEnOn_A	12468774	1107	0	0
gen_assertions[0].RstNOff_A	12468774	13788	0	0
gen_assertions[0].RstNOn_A	12468774	1107	0	0
gen_assertions[1].RstEnOff_A	49875289	12527	0	0
gen_assertions[1].RstEnOn_A	49875289	1048	0	0
gen_assertions[1].RstNOff_A	49875289	12527	0	0
gen_assertions[1].RstNOn_A	49875289	1048	0	0
gen_assertions[2].RstEnOff_A	24938140	12573	0	0
gen_assertions[2].RstEnOn_A	24938140	1038	0	0
gen_assertions[2].RstNOff_A	24938140	12573	0	0
gen_assertions[2].RstNOn_A	24938140	1038	0	0
gen_assertions[3].RstEnOff_A	24938221	12632	0	0
gen_assertions[3].RstEnOn_A	24938221	1092	0	0
gen_assertions[3].RstNOff_A	24938221	12632	0	0
gen_assertions[3].RstNOn_A	24938221	1092	0	0
gen_assertions[4].RstEnOff_A	1574662	21582	0	0
gen_assertions[4].RstEnOn_A	1574662	1142	0	0
gen_assertions[4].RstNOff_A	1574662	21582	0	0
gen_assertions[4].RstNOn_A	1574662	1142	0	0
gen_assertions[5].RstEnOff_A	12468774	14011	0	0
gen_assertions[5].RstEnOn_A	12468774	1181	0	0
gen_assertions[5].RstNOff_A	12468774	14011	0	0
gen_assertions[5].RstNOn_A	12468774	1181	0	0
gen_assertions[6].RstEnOff_A	12468774	14074	0	0
gen_assertions[6].RstEnOn_A	12468774	1245	0	0
gen_assertions[6].RstNOff_A	12468774	14074	0	0
gen_assertions[6].RstNOn_A	12468774	1245	0	0
gen_assertions[7].RstEnOff_A	12468774	14123	0	0
gen_assertions[7].RstEnOn_A	12468774	1297	0	0
gen_assertions[7].RstNOff_A	12468774	14123	0	0
gen_assertions[7].RstNOn_A	12468774	1297	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	13788	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	8	0	0
T6	3559	4	0	0
T7	295484	269	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1107	0	0
T5	3551	8	0	0
T6	3559	0	0	0
T7	295484	11	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T45	407213	0	0	0
T51	0	3	0	0
T57	0	1	0	0
T74	0	9	0	0
T75	0	8	0	0
T76	0	6	0	0
T77	0	1	0	0
T78	0	5	0	0
T79	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	13788	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	8	0	0
T6	3559	4	0	0
T7	295484	269	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1107	0	0
T5	3551	8	0	0
T6	3559	0	0	0
T7	295484	11	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T45	407213	0	0	0
T51	0	3	0	0
T57	0	1	0	0
T74	0	9	0	0
T75	0	8	0	0
T76	0	6	0	0
T77	0	1	0	0
T78	0	5	0	0
T79	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49875289	12527	0	0
T3	225743	66	0	0
T4	181157	69	0	0
T5	14209	7	0	0
T6	14238	4	0	0
T7	118188	240	0	0
T8	23351	0	0	0
T9	24469	4	0	0
T10	181295	63	0	0
T11	10960	4	0	0
T12	124100	35	0	0
T13	0	10	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49875289	1048	0	0
T5	14209	7	0	0
T6	14238	0	0	0
T7	118188	11	0	0
T8	23351	0	0	0
T9	24469	1	0	0
T10	181295	0	0	0
T11	10960	0	0	0
T12	124100	0	0	0
T13	15990	0	0	0
T27	0	17	0	0
T45	162882	0	0	0
T51	0	4	0	0
T74	0	10	0	0
T75	0	7	0	0
T76	0	4	0	0
T78	0	4	0	0
T80	0	18	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49875289	12527	0	0
T3	225743	66	0	0
T4	181157	69	0	0
T5	14209	7	0	0
T6	14238	4	0	0
T7	118188	240	0	0
T8	23351	0	0	0
T9	24469	4	0	0
T10	181295	63	0	0
T11	10960	4	0	0
T12	124100	35	0	0
T13	0	10	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49875289	1048	0	0
T5	14209	7	0	0
T6	14238	0	0	0
T7	118188	11	0	0
T8	23351	0	0	0
T9	24469	1	0	0
T10	181295	0	0	0
T11	10960	0	0	0
T12	124100	0	0	0
T13	15990	0	0	0
T27	0	17	0	0
T45	162882	0	0	0
T51	0	4	0	0
T74	0	10	0	0
T75	0	7	0	0
T76	0	4	0	0
T78	0	4	0	0
T80	0	18	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938140	12573	0	0
T3	112869	66	0	0
T4	90583	69	0	0
T5	7105	7	0	0
T6	7120	4	0	0
T7	590941	238	0	0
T8	11675	0	0	0
T9	12236	4	0	0
T10	90655	63	0	0
T11	5482	4	0	0
T12	62048	35	0	0
T13	0	10	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938140	1038	0	0
T5	7105	7	0	0
T6	7120	0	0	0
T7	590941	10	0	0
T8	11675	0	0	0
T9	12236	1	0	0
T10	90655	0	0	0
T11	5482	0	0	0
T12	62048	0	0	0
T13	7995	0	0	0
T27	0	17	0	0
T45	814475	0	0	0
T51	0	5	0	0
T57	0	1	0	0
T74	0	7	0	0
T75	0	8	0	0
T76	0	2	0	0
T79	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938140	12573	0	0
T3	112869	66	0	0
T4	90583	69	0	0
T5	7105	7	0	0
T6	7120	4	0	0
T7	590941	238	0	0
T8	11675	0	0	0
T9	12236	4	0	0
T10	90655	63	0	0
T11	5482	4	0	0
T12	62048	35	0	0
T13	0	10	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938140	1038	0	0
T5	7105	7	0	0
T6	7120	0	0	0
T7	590941	10	0	0
T8	11675	0	0	0
T9	12236	1	0	0
T10	90655	0	0	0
T11	5482	0	0	0
T12	62048	0	0	0
T13	7995	0	0	0
T27	0	17	0	0
T45	814475	0	0	0
T51	0	5	0	0
T57	0	1	0	0
T74	0	7	0	0
T75	0	8	0	0
T76	0	2	0	0
T79	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938221	12632	0	0
T3	112877	66	0	0
T4	90579	69	0	0
T5	7105	8	0	0
T6	7121	4	0	0
T7	590974	241	0	0
T8	11675	0	0	0
T9	12235	3	0	0
T10	90648	63	0	0
T11	5479	4	0	0
T12	62044	35	0	0
T13	0	10	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938221	1092	0	0
T5	7105	8	0	0
T6	7121	0	0	0
T7	590974	13	0	0
T8	11675	0	0	0
T9	12235	0	0	0
T10	90648	0	0	0
T11	5479	0	0	0
T12	62044	0	0	0
T13	7995	0	0	0
T27	0	20	0	0
T45	814507	0	0	0
T51	0	5	0	0
T52	0	9	0	0
T57	0	1	0	0
T74	0	7	0	0
T75	0	11	0	0
T80	0	22	0	0
T81	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938221	12632	0	0
T3	112877	66	0	0
T4	90579	69	0	0
T5	7105	8	0	0
T6	7121	4	0	0
T7	590974	241	0	0
T8	11675	0	0	0
T9	12235	3	0	0
T10	90648	63	0	0
T11	5479	4	0	0
T12	62044	35	0	0
T13	0	10	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24938221	1092	0	0
T5	7105	8	0	0
T6	7121	0	0	0
T7	590974	13	0	0
T8	11675	0	0	0
T9	12235	0	0	0
T10	90648	0	0	0
T11	5479	0	0	0
T12	62044	0	0	0
T13	7995	0	0	0
T27	0	20	0	0
T45	814507	0	0	0
T51	0	5	0	0
T52	0	9	0	0
T57	0	1	0	0
T74	0	7	0	0
T75	0	11	0	0
T80	0	22	0	0
T81	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	21582	0	0
T1	731	3	0	0
T2	728	3	0	0
T3	7070	98	0	0
T4	5675	95	0	0
T5	442	12	0	0
T6	444	6	0	0
T7	37366	388	0	0
T8	731	3	0	0
T9	763	7	0	0
T10	5681	89	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	1142	0	0
T5	442	11	0	0
T6	444	0	0	0
T7	37366	13	0	0
T8	731	0	0	0
T9	763	1	0	0
T10	5681	0	0	0
T11	342	0	0	0
T12	3920	0	0	0
T13	499	0	0	0
T14	0	1	0	0
T27	0	17	0	0
T29	0	1	0	0
T45	51148	0	0	0
T51	0	8	0	0
T74	0	7	0	0
T75	0	11	0	0
T80	0	22	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	21582	0	0
T1	731	3	0	0
T2	728	3	0	0
T3	7070	98	0	0
T4	5675	95	0	0
T5	442	12	0	0
T6	444	6	0	0
T7	37366	388	0	0
T8	731	3	0	0
T9	763	7	0	0
T10	5681	89	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1574662	1142	0	0
T5	442	11	0	0
T6	444	0	0	0
T7	37366	13	0	0
T8	731	0	0	0
T9	763	1	0	0
T10	5681	0	0	0
T11	342	0	0	0
T12	3920	0	0	0
T13	499	0	0	0
T14	0	1	0	0
T27	0	17	0	0
T29	0	1	0	0
T45	51148	0	0	0
T51	0	8	0	0
T74	0	7	0	0
T75	0	11	0	0
T80	0	22	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	14011	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	9	0	0
T6	3559	4	0	0
T7	295484	270	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1181	0	0
T5	3551	9	0	0
T6	3559	0	0	0
T7	295484	12	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T27	0	16	0	0
T29	0	1	0	0
T45	407213	0	0	0
T51	0	8	0	0
T52	0	9	0	0
T74	0	7	0	0
T75	0	10	0	0
T80	0	22	0	0
T81	0	14	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	14011	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	9	0	0
T6	3559	4	0	0
T7	295484	270	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1181	0	0
T5	3551	9	0	0
T6	3559	0	0	0
T7	295484	12	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T27	0	16	0	0
T29	0	1	0	0
T45	407213	0	0	0
T51	0	8	0	0
T52	0	9	0	0
T74	0	7	0	0
T75	0	10	0	0
T80	0	22	0	0
T81	0	14	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	14074	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	14	0	0
T6	3559	4	0	0
T7	295484	270	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1245	0	0
T5	3551	14	0	0
T6	3559	0	0	0
T7	295484	12	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T27	0	14	0	0
T45	407213	0	0	0
T51	0	9	0	0
T52	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T79	0	1	0	0
T80	0	24	0	0
T81	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	14074	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	14	0	0
T6	3559	4	0	0
T7	295484	270	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1245	0	0
T5	3551	14	0	0
T6	3559	0	0	0
T7	295484	12	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T27	0	14	0	0
T45	407213	0	0	0
T51	0	9	0	0
T52	0	10	0	0
T74	0	10	0	0
T75	0	10	0	0
T79	0	1	0	0
T80	0	24	0	0
T81	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	14123	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	15	0	0
T6	3559	4	0	0
T7	295484	266	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1297	0	0
T5	3551	15	0	0
T6	3559	0	0	0
T7	295484	8	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T27	0	17	0	0
T29	0	1	0	0
T45	407213	0	0	0
T51	0	10	0	0
T52	0	13	0	0
T74	0	9	0	0
T75	0	8	0	0
T80	0	21	0	0
T81	0	14	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	14123	0	0
T3	56447	75	0	0
T4	45297	75	0	0
T5	3551	15	0	0
T6	3559	4	0	0
T7	295484	266	0	0
T8	5835	0	0	0
T9	6117	4	0	0
T10	45326	75	0	0
T11	2741	4	0	0
T12	31024	35	0	0
T13	0	12	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12468774	1297	0	0
T5	3551	15	0	0
T6	3559	0	0	0
T7	295484	8	0	0
T8	5835	0	0	0
T9	6117	0	0	0
T10	45326	0	0	0
T11	2741	0	0	0
T12	31024	0	0	0
T13	3996	0	0	0
T27	0	17	0	0
T29	0	1	0	0
T45	407213	0	0	0
T51	0	10	0	0
T52	0	13	0	0
T74	0	9	0	0
T75	0	8	0	0
T80	0	21	0	0
T81	0	14	0	0