Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11733875	8650	0	0
alert_regwen_rd_A	11733875	3870	0	0
cpu_regwen_rd_A	11733875	3795	0	0
sw_rst_ctrl_n_0_rd_A	11733875	9261	0	0
sw_rst_ctrl_n_1_rd_A	11733875	9779	0	0
sw_rst_ctrl_n_2_rd_A	11733875	9566	0	0
sw_rst_ctrl_n_3_rd_A	11733875	9371	0	0
sw_rst_ctrl_n_4_rd_A	11733875	9576	0	0
sw_rst_ctrl_n_5_rd_A	11733875	9710	0	0
sw_rst_ctrl_n_6_rd_A	11733875	9800	0	0
sw_rst_ctrl_n_7_rd_A	11733875	9299	0	0
sw_rst_regwen_0_rd_A	11733875	4660	0	0
sw_rst_regwen_1_rd_A	11733875	4652	0	0
sw_rst_regwen_2_rd_A	11733875	4502	0	0
sw_rst_regwen_3_rd_A	11733875	4666	0	0
sw_rst_regwen_4_rd_A	11733875	4617	0	0
sw_rst_regwen_5_rd_A	11733875	4715	0	0
sw_rst_regwen_6_rd_A	11733875	4808	0	0
sw_rst_regwen_7_rd_A	11733875	4521	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	8650	0	0
T58	3348	395	0	0
T59	10914	610	0	0
T60	3154	189	0	0
T61	9210	1	0	0
T67	2724	46	0	0
T68	21507	3	0	0
T83	3958	136	0	0
T84	6998	267	0	0
T85	8302	413	0	0
T86	10475	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	3870	0	0
T7	264724	329	0	0
T8	5099	0	0	0
T9	5826	0	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T45	370246	0	0	0
T71	5478	0	0	0
T75	0	66	0	0
T91	0	37	0	0
T94	0	87	0	0
T97	0	62	0	0
T98	0	88	0	0
T116	0	42	0	0
T117	0	24	0	0
T118	0	58	0	0
T119	0	68	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	3795	0	0
T7	264724	287	0	0
T8	5099	0	0	0
T9	5826	0	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T45	370246	0	0	0
T71	5478	0	0	0
T75	0	53	0	0
T91	0	31	0	0
T94	0	94	0	0
T97	0	77	0	0
T98	0	74	0	0
T116	0	22	0	0
T117	0	23	0	0
T118	0	63	0	0
T119	0	80	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9261	0	0
T7	264724	483	0	0
T8	5099	0	0	0
T9	5826	16	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	74	0	0
T29	0	21	0	0
T45	370246	0	0	0
T51	0	141	0	0
T71	5478	0	0	0
T75	0	166	0	0
T91	0	30	0	0
T120	0	17	0	0
T121	0	19	0	0
T122	0	5	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9779	0	0
T7	264724	489	0	0
T8	5099	0	0	0
T9	5826	12	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	44	0	0
T29	0	15	0	0
T45	370246	0	0	0
T51	0	173	0	0
T71	5478	0	0	0
T75	0	166	0	0
T91	0	40	0	0
T120	0	5	0	0
T121	0	10	0	0
T122	0	4	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9566	0	0
T7	264724	456	0	0
T8	5099	0	0	0
T9	5826	21	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	43	0	0
T29	0	10	0	0
T45	370246	0	0	0
T51	0	169	0	0
T71	5478	0	0	0
T75	0	180	0	0
T91	0	37	0	0
T120	0	24	0	0
T121	0	11	0	0
T122	0	9	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9371	0	0
T7	264724	492	0	0
T8	5099	0	0	0
T9	5826	24	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	44	0	0
T29	0	18	0	0
T45	370246	0	0	0
T51	0	158	0	0
T71	5478	0	0	0
T75	0	148	0	0
T91	0	16	0	0
T120	0	13	0	0
T121	0	10	0	0
T122	0	3	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9576	0	0
T7	264724	538	0	0
T8	5099	0	0	0
T9	5826	11	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	30	0	0
T29	0	14	0	0
T45	370246	0	0	0
T51	0	146	0	0
T71	5478	0	0	0
T75	0	177	0	0
T91	0	47	0	0
T120	0	6	0	0
T121	0	16	0	0
T122	0	12	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9710	0	0
T7	264724	516	0	0
T8	5099	0	0	0
T9	5826	16	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	50	0	0
T29	0	17	0	0
T45	370246	0	0	0
T51	0	148	0	0
T71	5478	0	0	0
T75	0	170	0	0
T91	0	38	0	0
T120	0	7	0	0
T121	0	6	0	0
T122	0	8	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9800	0	0
T7	264724	498	0	0
T8	5099	0	0	0
T9	5826	14	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	80	0	0
T29	0	11	0	0
T45	370246	0	0	0
T51	0	180	0	0
T71	5478	0	0	0
T75	0	197	0	0
T91	0	21	0	0
T120	0	19	0	0
T121	0	18	0	0
T122	0	4	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	9299	0	0
T7	264724	461	0	0
T8	5099	0	0	0
T9	5826	10	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T25	0	53	0	0
T29	0	18	0	0
T45	370246	0	0	0
T51	0	147	0	0
T71	5478	0	0	0
T75	0	170	0	0
T91	0	34	0	0
T120	0	11	0	0
T121	0	9	0	0
T123	0	16	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4660	0	0
T7	264724	372	0	0
T8	5099	0	0	0
T9	5826	9	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	12	0	0
T45	370246	0	0	0
T51	0	35	0	0
T71	5478	0	0	0
T75	0	59	0	0
T91	0	10	0	0
T120	0	16	0	0
T121	0	7	0	0
T123	0	4	0	0
T124	0	8	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4652	0	0
T7	264724	309	0	0
T8	5099	0	0	0
T9	5826	8	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	5	0	0
T45	370246	0	0	0
T51	0	34	0	0
T71	5478	0	0	0
T75	0	60	0	0
T91	0	32	0	0
T120	0	10	0	0
T121	0	15	0	0
T123	0	3	0	0
T124	0	8	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4502	0	0
T7	264724	311	0	0
T8	5099	0	0	0
T9	5826	0	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	6	0	0
T45	370246	0	0	0
T51	0	45	0	0
T71	5478	0	0	0
T75	0	58	0	0
T91	0	31	0	0
T94	0	80	0	0
T120	0	10	0	0
T121	0	8	0	0
T123	0	8	0	0
T124	0	11	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4666	0	0
T7	264724	317	0	0
T8	5099	0	0	0
T9	5826	5	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	3	0	0
T45	370246	0	0	0
T51	0	48	0	0
T71	5478	0	0	0
T75	0	62	0	0
T91	0	31	0	0
T120	0	5	0	0
T121	0	5	0	0
T123	0	8	0	0
T124	0	11	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4617	0	0
T7	264724	359	0	0
T8	5099	0	0	0
T9	5826	7	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	7	0	0
T45	370246	0	0	0
T51	0	37	0	0
T71	5478	0	0	0
T75	0	75	0	0
T91	0	23	0	0
T120	0	9	0	0
T121	0	5	0	0
T123	0	13	0	0
T124	0	11	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4715	0	0
T7	264724	308	0	0
T8	5099	0	0	0
T9	5826	6	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	2	0	0
T45	370246	0	0	0
T51	0	38	0	0
T71	5478	0	0	0
T75	0	55	0	0
T91	0	37	0	0
T120	0	9	0	0
T121	0	9	0	0
T123	0	3	0	0
T124	0	9	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4808	0	0
T7	264724	354	0	0
T8	5099	0	0	0
T9	5826	4	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	9	0	0
T45	370246	0	0	0
T51	0	27	0	0
T71	5478	0	0	0
T75	0	54	0	0
T91	0	41	0	0
T120	0	10	0	0
T121	0	7	0	0
T123	0	3	0	0
T124	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11733875	4521	0	0
T7	264724	356	0	0
T8	5099	0	0	0
T9	5826	10	0	0
T10	42163	0	0	0
T11	2455	0	0	0
T12	26196	0	0	0
T13	3145	0	0	0
T14	4480	0	0	0
T29	0	2	0	0
T45	370246	0	0	0
T51	0	31	0	0
T71	5478	0	0	0
T75	0	42	0	0
T91	0	25	0	0
T120	0	8	0	0
T121	0	9	0	0
T123	0	6	0	0
T124	0	8	0	0