Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

362817

1

T1

1095

T2

66

T4

275

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	516342	1			T1	1500		T2	80		T3	10
values[0x0]	226375	1			T1	808		T2	38		T4	168
values[0x1]	225974	1			T1	892		T2	49		T4	181

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	508792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

459899

1

T1

1427

T2

84

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3372	1			T1	18		T4	3		T7	1
valid_sources[0x01]	3060	1			T1	11		T4	3		T5	1
valid_sources[0x02]	6484	1			T1	13		T2	5		T4	1
valid_sources[0x03]	3185	1			T1	18		T4	4		T10	61
valid_sources[0x04]	7310	1			T1	9		T2	2		T10	64
valid_sources[0x05]	3089	1			T1	20		T4	7		T7	1
valid_sources[0x06]	4980	1			T1	11		T4	5		T7	1
valid_sources[0x07]	3865	1			T1	11		T4	5		T6	1
valid_sources[0x08]	3618	1			T1	11		T4	4		T7	2
valid_sources[0x09]	3272	1			T1	11		T4	3		T7	3
valid_sources[0x0a]	3365	1			T1	10		T4	4		T10	75
valid_sources[0x0b]	3365	1			T1	12		T10	43		T11	4
valid_sources[0x0c]	3393	1			T1	17		T2	6		T4	1
valid_sources[0x0d]	3203	1			T1	9		T4	3		T7	4
valid_sources[0x0e]	3480	1			T1	12		T4	4		T7	1
valid_sources[0x0f]	3568	1			T1	11		T4	3		T10	50
valid_sources[0x10]	4480	1			T1	16		T4	2		T10	41
valid_sources[0x11]	4399	1			T1	10		T4	3		T6	1
valid_sources[0x12]	3437	1			T1	11		T4	3		T10	69
valid_sources[0x13]	3022	1			T1	12		T4	4		T10	57
valid_sources[0x14]	3822	1			T1	17		T4	9		T6	1
valid_sources[0x15]	3642	1			T1	14		T4	1		T7	2
valid_sources[0x16]	4113	1			T1	15		T4	3		T7	1
valid_sources[0x17]	3370	1			T1	12		T4	2		T10	44
valid_sources[0x18]	3380	1			T1	10		T4	4		T7	1
valid_sources[0x19]	6544	1			T1	12		T4	3		T7	1
valid_sources[0x1a]	3405	1			T1	13		T2	5		T4	1
valid_sources[0x1b]	3221	1			T1	14		T4	2		T6	1
valid_sources[0x1c]	3447	1			T1	16		T4	2		T7	1
valid_sources[0x1d]	3201	1			T1	20		T4	3		T10	54
valid_sources[0x1e]	3497	1			T1	9		T7	1		T10	51
valid_sources[0x1f]	3346	1			T1	11		T2	1		T4	2
valid_sources[0x20]	3408	1			T1	12		T4	4		T7	2
valid_sources[0x21]	3137	1			T1	9		T4	4		T10	50
valid_sources[0x22]	3549	1			T1	10		T7	1		T10	46
valid_sources[0x23]	3249	1			T1	17		T4	4		T7	1
valid_sources[0x24]	3370	1			T1	17		T4	2		T10	71
valid_sources[0x25]	3698	1			T1	10		T2	4		T4	3
valid_sources[0x26]	3563	1			T1	10		T2	2		T4	2
valid_sources[0x27]	3570	1			T1	16		T4	3		T7	3
valid_sources[0x28]	3085	1			T1	11		T3	1		T4	3
valid_sources[0x29]	3341	1			T1	24		T2	3		T4	3
valid_sources[0x2a]	3271	1			T1	11		T4	2		T6	1
valid_sources[0x2b]	3684	1			T1	22		T2	1		T4	2
valid_sources[0x2c]	3865	1			T1	10		T4	1		T7	1
valid_sources[0x2d]	3689	1			T1	15		T2	2		T6	1
valid_sources[0x2e]	7635	1			T1	8		T2	3		T4	3
valid_sources[0x2f]	3850	1			T1	10		T4	3		T10	66
valid_sources[0x30]	3512	1			T1	10		T2	1		T4	2
valid_sources[0x31]	3319	1			T1	12		T4	2		T10	44
valid_sources[0x32]	4471	1			T1	13		T4	4		T10	63
valid_sources[0x33]	3648	1			T1	13		T4	3		T6	1
valid_sources[0x34]	7404	1			T1	9		T4	4		T7	1
valid_sources[0x35]	3376	1			T1	17		T4	6		T7	1
valid_sources[0x36]	4910	1			T1	19		T4	2		T7	1
valid_sources[0x37]	3434	1			T1	10		T4	10		T7	1
valid_sources[0x38]	3257	1			T1	20		T4	6		T10	52
valid_sources[0x39]	3011	1			T1	15		T2	2		T4	4
valid_sources[0x3a]	3302	1			T1	12		T4	4		T7	2
valid_sources[0x3b]	4637	1			T1	11		T8	70		T10	49
valid_sources[0x3c]	3551	1			T1	12		T4	3		T10	58
valid_sources[0x3d]	3830	1			T1	9		T2	1		T4	5
valid_sources[0x3e]	3103	1			T1	10		T4	3		T7	1
valid_sources[0x3f]	3397	1			T1	17		T4	1		T10	51
valid_sources[0x40]	3338	1			T1	15		T2	6		T4	2
valid_sources[0x41]	3720	1			T1	14		T4	3		T7	1
valid_sources[0x42]	3484	1			T1	15		T4	5		T7	1
valid_sources[0x43]	3029	1			T1	9		T4	2		T10	60
valid_sources[0x44]	3345	1			T1	11		T4	4		T7	2
valid_sources[0x45]	4150	1			T1	4		T2	1		T4	1
valid_sources[0x46]	3428	1			T1	12		T4	3		T7	1
valid_sources[0x47]	3425	1			T1	10		T4	5		T6	1
valid_sources[0x48]	3618	1			T1	14		T4	6		T7	1
valid_sources[0x49]	4121	1			T1	12		T4	2		T7	2
valid_sources[0x4a]	3304	1			T1	7		T2	4		T10	60
valid_sources[0x4b]	4213	1			T1	15		T4	4		T8	538
valid_sources[0x4c]	4282	1			T1	15		T4	2		T7	1
valid_sources[0x4d]	3408	1			T1	9		T4	4		T7	1
valid_sources[0x4e]	4559	1			T1	10		T4	3		T10	45
valid_sources[0x4f]	3495	1			T1	12		T4	3		T7	2
valid_sources[0x50]	3192	1			T1	11		T4	3		T7	3
valid_sources[0x51]	3416	1			T1	9		T2	1		T4	3
valid_sources[0x52]	3430	1			T1	14		T4	3		T10	55
valid_sources[0x53]	3168	1			T1	7		T2	1		T4	1
valid_sources[0x54]	3982	1			T1	11		T2	4		T4	2
valid_sources[0x55]	3532	1			T1	10		T4	2		T10	66
valid_sources[0x56]	3724	1			T1	13		T4	3		T7	1
valid_sources[0x57]	3693	1			T1	7		T4	1		T10	54
valid_sources[0x58]	3567	1			T1	11		T2	1		T4	2
valid_sources[0x59]	3279	1			T1	9		T4	2		T7	1
valid_sources[0x5a]	4198	1			T1	6		T4	1		T10	56
valid_sources[0x5b]	3857	1			T1	11		T4	3		T7	1
valid_sources[0x5c]	2937	1			T1	13		T4	5		T10	74
valid_sources[0x5d]	3070	1			T1	10		T2	5		T4	2
valid_sources[0x5e]	3383	1			T1	18		T4	4		T7	1
valid_sources[0x5f]	3381	1			T1	12		T4	4		T7	1
valid_sources[0x60]	6519	1			T1	11		T4	4		T7	1
valid_sources[0x61]	3512	1			T1	9		T4	8		T7	1
valid_sources[0x62]	2977	1			T1	13		T4	1		T6	1
valid_sources[0x63]	3381	1			T1	16		T4	1		T7	1
valid_sources[0x64]	3677	1			T1	15		T4	2		T7	2
valid_sources[0x65]	3980	1			T1	12		T4	2		T10	63
valid_sources[0x66]	5334	1			T1	13		T4	3		T7	2
valid_sources[0x67]	3509	1			T1	8		T4	1		T7	1
valid_sources[0x68]	3507	1			T1	13		T4	2		T7	1
valid_sources[0x69]	3225	1			T1	15		T4	2		T7	4
valid_sources[0x6a]	3232	1			T1	12		T4	4		T10	58
valid_sources[0x6b]	6648	1			T1	5		T4	5		T6	1
valid_sources[0x6c]	4128	1			T1	15		T4	3		T7	3
valid_sources[0x6d]	4735	1			T1	14		T2	1		T3	9
valid_sources[0x6e]	3506	1			T1	12		T4	3		T10	75
valid_sources[0x6f]	3202	1			T1	11		T4	1		T10	44
valid_sources[0x70]	6395	1			T1	15		T2	1		T4	1
valid_sources[0x71]	3778	1			T1	16		T4	2		T10	48
valid_sources[0x72]	4221	1			T1	11		T4	1		T7	1
valid_sources[0x73]	3689	1			T1	8		T4	2		T7	1
valid_sources[0x74]	3768	1			T1	9		T2	2		T4	6
valid_sources[0x75]	4008	1			T1	16		T2	1		T4	4
valid_sources[0x76]	3244	1			T1	6		T4	4		T7	1
valid_sources[0x77]	3691	1			T1	16		T6	2		T7	3
valid_sources[0x78]	3787	1			T1	12		T4	1		T10	56
valid_sources[0x79]	3084	1			T1	13		T2	2		T4	6
valid_sources[0x7a]	3109	1			T1	18		T4	1		T10	68
valid_sources[0x7b]	5040	1			T1	13		T4	11		T10	64
valid_sources[0x7c]	6990	1			T1	12		T4	7		T7	2
valid_sources[0x7d]	4464	1			T1	9		T4	7		T7	2
valid_sources[0x7e]	3879	1			T1	15		T4	3		T6	2
valid_sources[0x7f]	4327	1			T1	26		T4	4		T7	1
valid_sources[0x80]	5112	1			T1	7		T4	3		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

242210

1

T1

677

T2

44

T4

190

values[0x0]

all_enables

biggest_size

78851

1

T1

277

T2

14

T4

58

values[0x1]

all_enables

biggest_size

41756

1

T1

141

T2

8

T4

27