Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T8,T10,T23
1	0	Covered	T8,T10,T14

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T7,T8,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52239799	9007	0	0
CascadeEffAonToRstPorAboveRise_A	52239799	9007	0	0
CascadeEffAonToRstPorIoAboveFall_A	50148691	9007	0	0
CascadeEffAonToRstPorIoAboveRise_A	50148691	9007	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25075253	9007	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25075253	9007	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12537271	9007	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12537271	9007	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25075173	9007	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25075173	9007	0	0
CascadeLcToLcAboveFall_A	52239799	21933	0	0
CascadeLcToLcAboveRise_A	52239799	21933	0	0
CascadeLcToLcAonAboveFall_A	1583781	21933	0	0
CascadeLcToLcAonAboveRise_A	1583781	21933	0	0
CascadeLcToLcShadowedAboveFall_A	52239799	21933	0	0
CascadeLcToLcShadowedAboveRise_A	52239799	21933	0	0
CascadePorToAonAboveFall_A	1583781	7279	0	0
CascadeSysToSysAboveFall_A	52239799	21933	0	0
CascadeSysToSysAboveRise_A	52239799	21933	0	0
ScanRstToAonRise_A	1583781	215	0	0
StablePorToAonRise_A	1583781	9007	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11041913	21933	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11041913	21933	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11041913	21933	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11041913	21933	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12537271	21933	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12537271	21933	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11041913	21933	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11041913	21933	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11041913	21933	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11041913	21933	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	9007	0	0
T1	122241	27	0	0
T2	9848	1	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	2	0	0
T8	166335	18	0	0
T9	7714	1	0	0
T10	426112	82	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	9007	0	0
T1	122241	27	0	0
T2	9848	1	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	2	0	0
T8	166335	18	0	0
T9	7714	1	0	0
T10	426112	82	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50148691	9007	0	0
T1	117396	27	0	0
T2	9453	1	0	0
T3	858179	271	0	0
T4	26433	1	0	0
T5	20411	2	0	0
T6	7678	1	0	0
T7	13648	2	0	0
T8	159679	18	0	0
T9	7406	1	0	0
T10	409013	82	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50148691	9007	0	0
T1	117396	27	0	0
T2	9453	1	0	0
T3	858179	271	0	0
T4	26433	1	0	0
T5	20411	2	0	0
T6	7678	1	0	0
T7	13648	2	0	0
T8	159679	18	0	0
T9	7406	1	0	0
T10	409013	82	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075253	9007	0	0
T1	58690	27	0	0
T2	4726	1	0	0
T3	429078	271	0	0
T4	13216	1	0	0
T5	10205	2	0	0
T6	3839	1	0	0
T7	6827	2	0	0
T8	79833	18	0	0
T9	3702	1	0	0
T10	204511	82	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075253	9007	0	0
T1	58690	27	0	0
T2	4726	1	0	0
T3	429078	271	0	0
T4	13216	1	0	0
T5	10205	2	0	0
T6	3839	1	0	0
T7	6827	2	0	0
T8	79833	18	0	0
T9	3702	1	0	0
T10	204511	82	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	9007	0	0
T1	29352	27	0	0
T2	2363	1	0	0
T3	214526	271	0	0
T4	6607	1	0	0
T5	5101	2	0	0
T6	1918	1	0	0
T7	3413	2	0	0
T8	39911	18	0	0
T9	1849	1	0	0
T10	102253	82	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	9007	0	0
T1	29352	27	0	0
T2	2363	1	0	0
T3	214526	271	0	0
T4	6607	1	0	0
T5	5101	2	0	0
T6	1918	1	0	0
T7	3413	2	0	0
T8	39911	18	0	0
T9	1849	1	0	0
T10	102253	82	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075173	9007	0	0
T1	58705	27	0	0
T2	4726	1	0	0
T3	429094	271	0	0
T4	13217	1	0	0
T5	10206	2	0	0
T6	3839	1	0	0
T7	6825	2	0	0
T8	79834	18	0	0
T9	3702	1	0	0
T10	204499	82	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075173	9007	0	0
T1	58705	27	0	0
T2	4726	1	0	0
T3	429094	271	0	0
T4	13217	1	0	0
T5	10206	2	0	0
T6	3839	1	0	0
T7	6825	2	0	0
T8	79834	18	0	0
T9	3702	1	0	0
T10	204499	82	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	21933	0	0
T1	122241	102	0	0
T2	9848	9	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	6	0	0
T8	166335	64	0	0
T9	7714	1	0	0
T10	426112	260	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	21933	0	0
T1	122241	102	0	0
T2	9848	9	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	6	0	0
T8	166335	64	0	0
T9	7714	1	0	0
T10	426112	260	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	21933	0	0
T1	3682	102	0	0
T2	295	9	0	0
T3	26941	271	0	0
T4	825	1	0	0
T5	637	2	0	0
T6	239	1	0	0
T7	426	6	0	0
T8	5110	64	0	0
T9	230	1	0	0
T10	13062	260	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	21933	0	0
T1	3682	102	0	0
T2	295	9	0	0
T3	26941	271	0	0
T4	825	1	0	0
T5	637	2	0	0
T6	239	1	0	0
T7	426	6	0	0
T8	5110	64	0	0
T9	230	1	0	0
T10	13062	260	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	21933	0	0
T1	122241	102	0	0
T2	9848	9	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	6	0	0
T8	166335	64	0	0
T9	7714	1	0	0
T10	426112	260	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	21933	0	0
T1	122241	102	0	0
T2	9848	9	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	6	0	0
T8	166335	64	0	0
T9	7714	1	0	0
T10	426112	260	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	7279	0	0
T1	3682	27	0	0
T2	295	1	0	0
T3	26941	271	0	0
T4	825	1	0	0
T5	637	21	0	0
T6	239	1	0	0
T7	426	1	0	0
T8	5110	11	0	0
T9	230	1	0	0
T10	13062	31	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	21933	0	0
T1	122241	102	0	0
T2	9848	9	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	6	0	0
T8	166335	64	0	0
T9	7714	1	0	0
T10	426112	260	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52239799	21933	0	0
T1	122241	102	0	0
T2	9848	9	0	0
T3	893973	271	0	0
T4	27535	1	0	0
T5	21262	2	0	0
T6	7997	1	0	0
T7	14224	6	0	0
T8	166335	64	0	0
T9	7714	1	0	0
T10	426112	260	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	215	0	0
T8	5110	1	0	0
T9	230	0	0	0
T10	13062	4	0	0
T11	486	0	0	0
T12	460	0	0	0
T13	217	0	0	0
T14	737	0	0	0
T15	695	0	0	0
T23	16528	1	0	0
T24	0	6	0	0
T25	734	0	0	0
T50	0	3	0	0
T52	0	2	0	0
T53	0	7	0	0
T54	0	5	0	0
T87	0	6	0	0
T88	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	9007	0	0
T1	3682	27	0	0
T2	295	1	0	0
T3	26941	271	0	0
T4	825	1	0	0
T5	637	2	0	0
T6	239	1	0	0
T7	426	2	0	0
T8	5110	18	0	0
T9	230	1	0	0
T10	13062	82	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	21933	0	0
T1	29352	102	0	0
T2	2363	9	0	0
T3	214526	271	0	0
T4	6607	1	0	0
T5	5101	2	0	0
T6	1918	1	0	0
T7	3413	6	0	0
T8	39911	64	0	0
T9	1849	1	0	0
T10	102253	260	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	21933	0	0
T1	29352	102	0	0
T2	2363	9	0	0
T3	214526	271	0	0
T4	6607	1	0	0
T5	5101	2	0	0
T6	1918	1	0	0
T7	3413	6	0	0
T8	39911	64	0	0
T9	1849	1	0	0
T10	102253	260	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11041913	21933	0	0
T1	26189	102	0	0
T2	1775	9	0	0
T3	209039	271	0	0
T4	6541	1	0	0
T5	5036	2	0	0
T6	1828	1	0	0
T7	3265	6	0	0
T8	34773	64	0	0
T9	1760	1	0	0
T10	82675	260	0	0