Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12537271	13903	0	0
gen_assertions[0].RstEnOn_A	12537271	1156	0	0
gen_assertions[0].RstNOff_A	12537271	13903	0	0
gen_assertions[0].RstNOn_A	12537271	1156	0	0
gen_assertions[1].RstEnOff_A	50148691	12639	0	0
gen_assertions[1].RstEnOn_A	50148691	1093	0	0
gen_assertions[1].RstNOff_A	50148691	12639	0	0
gen_assertions[1].RstNOn_A	50148691	1093	0	0
gen_assertions[2].RstEnOff_A	25075253	12676	0	0
gen_assertions[2].RstEnOn_A	25075253	1075	0	0
gen_assertions[2].RstNOff_A	25075253	12676	0	0
gen_assertions[2].RstNOn_A	25075253	1075	0	0
gen_assertions[3].RstEnOff_A	25075173	12753	0	0
gen_assertions[3].RstEnOn_A	25075173	1142	0	0
gen_assertions[3].RstNOff_A	25075173	12753	0	0
gen_assertions[3].RstNOn_A	25075173	1142	0	0
gen_assertions[4].RstEnOff_A	1583781	21656	0	0
gen_assertions[4].RstEnOn_A	1583781	1181	0	0
gen_assertions[4].RstNOff_A	1583781	21656	0	0
gen_assertions[4].RstNOn_A	1583781	1181	0	0
gen_assertions[5].RstEnOff_A	12537271	14109	0	0
gen_assertions[5].RstEnOn_A	12537271	1218	0	0
gen_assertions[5].RstNOff_A	12537271	14109	0	0
gen_assertions[5].RstNOn_A	12537271	1218	0	0
gen_assertions[6].RstEnOff_A	12537271	14174	0	0
gen_assertions[6].RstEnOn_A	12537271	1286	0	0
gen_assertions[6].RstNOff_A	12537271	14174	0	0
gen_assertions[6].RstNOn_A	12537271	1286	0	0
gen_assertions[7].RstEnOff_A	12537271	14189	0	0
gen_assertions[7].RstEnOn_A	12537271	1310	0	0
gen_assertions[7].RstNOff_A	12537271	14189	0	0
gen_assertions[7].RstNOn_A	12537271	1310	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	13903	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	2	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	50	0	0
T9	1849	0	0	0
T10	102253	208	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	5	0	0
T23	0	115	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1156	0	0
T2	2363	2	0	0
T3	214526	0	0	0
T4	6607	2	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	5	0	0
T9	1849	0	0	0
T10	102253	31	0	0
T11	3909	3	0	0
T14	0	1	0	0
T23	0	10	0	0
T24	0	31	0	0
T61	0	2	0	0
T68	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	13903	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	2	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	50	0	0
T9	1849	0	0	0
T10	102253	208	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	5	0	0
T23	0	115	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1156	0	0
T2	2363	2	0	0
T3	214526	0	0	0
T4	6607	2	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	5	0	0
T9	1849	0	0	0
T10	102253	31	0	0
T11	3909	3	0	0
T14	0	1	0	0
T23	0	10	0	0
T24	0	31	0	0
T61	0	2	0	0
T68	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50148691	12639	0	0
T1	117396	66	0	0
T2	9453	8	0	0
T3	858179	0	0	0
T4	26433	2	0	0
T5	20411	0	0	0
T6	7678	0	0	0
T7	13648	4	0	0
T8	159679	47	0	0
T9	7406	0	0	0
T10	409013	189	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	3	0	0
T23	0	103	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50148691	1093	0	0
T2	9453	2	0	0
T3	858179	0	0	0
T4	26433	2	0	0
T5	20411	0	0	0
T6	7678	0	0	0
T7	13648	0	0	0
T8	159679	6	0	0
T9	7406	0	0	0
T10	409013	29	0	0
T11	15637	0	0	0
T23	0	9	0	0
T24	0	29	0	0
T50	0	25	0	0
T52	0	2	0	0
T53	0	21	0	0
T61	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50148691	12639	0	0
T1	117396	66	0	0
T2	9453	8	0	0
T3	858179	0	0	0
T4	26433	2	0	0
T5	20411	0	0	0
T6	7678	0	0	0
T7	13648	4	0	0
T8	159679	47	0	0
T9	7406	0	0	0
T10	409013	189	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	3	0	0
T23	0	103	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50148691	1093	0	0
T2	9453	2	0	0
T3	858179	0	0	0
T4	26433	2	0	0
T5	20411	0	0	0
T6	7678	0	0	0
T7	13648	0	0	0
T8	159679	6	0	0
T9	7406	0	0	0
T10	409013	29	0	0
T11	15637	0	0	0
T23	0	9	0	0
T24	0	29	0	0
T50	0	25	0	0
T52	0	2	0	0
T53	0	21	0	0
T61	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075253	12676	0	0
T1	58690	66	0	0
T2	4726	8	0	0
T3	429078	0	0	0
T4	13216	3	0	0
T5	10205	0	0	0
T6	3839	0	0	0
T7	6827	4	0	0
T8	79833	45	0	0
T9	3702	0	0	0
T10	204511	187	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	3	0	0
T23	0	107	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075253	1075	0	0
T4	13216	3	0	0
T5	10205	0	0	0
T6	3839	0	0	0
T7	6827	0	0	0
T8	79833	2	0	0
T9	3702	0	0	0
T10	204511	27	0	0
T11	7819	0	0	0
T12	7385	0	0	0
T13	3499	0	0	0
T23	0	13	0	0
T24	0	27	0	0
T50	0	32	0	0
T52	0	2	0	0
T53	0	21	0	0
T54	0	25	0	0
T61	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075253	12676	0	0
T1	58690	66	0	0
T2	4726	8	0	0
T3	429078	0	0	0
T4	13216	3	0	0
T5	10205	0	0	0
T6	3839	0	0	0
T7	6827	4	0	0
T8	79833	45	0	0
T9	3702	0	0	0
T10	204511	187	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	3	0	0
T23	0	107	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075253	1075	0	0
T4	13216	3	0	0
T5	10205	0	0	0
T6	3839	0	0	0
T7	6827	0	0	0
T8	79833	2	0	0
T9	3702	0	0	0
T10	204511	27	0	0
T11	7819	0	0	0
T12	7385	0	0	0
T13	3499	0	0	0
T23	0	13	0	0
T24	0	27	0	0
T50	0	32	0	0
T52	0	2	0	0
T53	0	21	0	0
T54	0	25	0	0
T61	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075173	12753	0	0
T1	58705	66	0	0
T2	4726	8	0	0
T3	429094	0	0	0
T4	13217	5	0	0
T5	10206	0	0	0
T6	3839	0	0	0
T7	6825	4	0	0
T8	79834	47	0	0
T9	3702	0	0	0
T10	204499	186	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	3	0	0
T23	0	105	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075173	1142	0	0
T4	13217	5	0	0
T5	10206	0	0	0
T6	3839	0	0	0
T7	6825	0	0	0
T8	79834	6	0	0
T9	3702	0	0	0
T10	204499	25	0	0
T11	7818	0	0	0
T12	7386	0	0	0
T13	3499	0	0	0
T23	0	11	0	0
T24	0	21	0	0
T50	0	30	0	0
T52	0	2	0	0
T53	0	21	0	0
T61	0	6	0	0
T68	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075173	12753	0	0
T1	58705	66	0	0
T2	4726	8	0	0
T3	429094	0	0	0
T4	13217	5	0	0
T5	10206	0	0	0
T6	3839	0	0	0
T7	6825	4	0	0
T8	79834	47	0	0
T9	3702	0	0	0
T10	204499	186	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	3	0	0
T23	0	105	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25075173	1142	0	0
T4	13217	5	0	0
T5	10206	0	0	0
T6	3839	0	0	0
T7	6825	0	0	0
T8	79834	6	0	0
T9	3702	0	0	0
T10	204499	25	0	0
T11	7818	0	0	0
T12	7386	0	0	0
T13	3499	0	0	0
T23	0	11	0	0
T24	0	21	0	0
T50	0	30	0	0
T52	0	2	0	0
T53	0	21	0	0
T61	0	6	0	0
T68	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	21656	0	0
T1	3682	77	0	0
T2	295	8	0	0
T3	26941	271	0	0
T4	825	7	0	0
T5	637	2	0	0
T6	239	1	0	0
T7	426	5	0	0
T8	5110	66	0	0
T9	230	1	0	0
T10	13062	277	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	1181	0	0
T4	825	6	0	0
T5	637	0	0	0
T6	239	0	0	0
T7	426	0	0	0
T8	5110	4	0	0
T9	230	0	0	0
T10	13062	28	0	0
T11	486	0	0	0
T12	460	0	0	0
T13	217	0	0	0
T23	0	8	0	0
T24	0	31	0	0
T50	0	28	0	0
T52	0	3	0	0
T53	0	18	0	0
T54	0	20	0	0
T61	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	21656	0	0
T1	3682	77	0	0
T2	295	8	0	0
T3	26941	271	0	0
T4	825	7	0	0
T5	637	2	0	0
T6	239	1	0	0
T7	426	5	0	0
T8	5110	66	0	0
T9	230	1	0	0
T10	13062	277	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583781	1181	0	0
T4	825	6	0	0
T5	637	0	0	0
T6	239	0	0	0
T7	426	0	0	0
T8	5110	4	0	0
T9	230	0	0	0
T10	13062	28	0	0
T11	486	0	0	0
T12	460	0	0	0
T13	217	0	0	0
T23	0	8	0	0
T24	0	31	0	0
T50	0	28	0	0
T52	0	3	0	0
T53	0	18	0	0
T54	0	20	0	0
T61	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	14109	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	7	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	49	0	0
T9	1849	0	0	0
T10	102253	204	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	4	0	0
T23	0	114	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1218	0	0
T4	6607	7	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	5	0	0
T9	1849	0	0	0
T10	102253	27	0	0
T11	3909	0	0	0
T12	3692	0	0	0
T13	1748	0	0	0
T23	0	9	0	0
T24	0	26	0	0
T50	0	27	0	0
T52	0	3	0	0
T53	0	23	0	0
T54	0	21	0	0
T61	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	14109	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	7	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	49	0	0
T9	1849	0	0	0
T10	102253	204	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	4	0	0
T23	0	114	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1218	0	0
T4	6607	7	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	5	0	0
T9	1849	0	0	0
T10	102253	27	0	0
T11	3909	0	0	0
T12	3692	0	0	0
T13	1748	0	0	0
T23	0	9	0	0
T24	0	26	0	0
T50	0	27	0	0
T52	0	3	0	0
T53	0	23	0	0
T54	0	21	0	0
T61	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	14174	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	50	0	0
T9	1849	0	0	0
T10	102253	203	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	5	0	0
T23	0	117	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1286	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	6	0	0
T9	1849	0	0	0
T10	102253	26	0	0
T11	3909	0	0	0
T12	3692	0	0	0
T13	1748	0	0	0
T14	0	1	0	0
T23	0	12	0	0
T24	0	27	0	0
T50	0	29	0	0
T52	0	3	0	0
T53	0	19	0	0
T61	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	14174	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	50	0	0
T9	1849	0	0	0
T10	102253	203	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	5	0	0
T23	0	117	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1286	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	6	0	0
T9	1849	0	0	0
T10	102253	26	0	0
T11	3909	0	0	0
T12	3692	0	0	0
T13	1748	0	0	0
T14	0	1	0	0
T23	0	12	0	0
T24	0	27	0	0
T50	0	29	0	0
T52	0	3	0	0
T53	0	19	0	0
T61	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	14189	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	49	0	0
T9	1849	0	0	0
T10	102253	200	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	4	0	0
T23	0	110	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1310	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	5	0	0
T9	1849	0	0	0
T10	102253	23	0	0
T11	3909	0	0	0
T12	3692	0	0	0
T13	1748	0	0	0
T23	0	6	0	0
T24	0	32	0	0
T50	0	23	0	0
T52	0	1	0	0
T53	0	19	0	0
T61	0	10	0	0
T68	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	14189	0	0
T1	29352	75	0	0
T2	2363	8	0	0
T3	214526	0	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	4	0	0
T8	39911	49	0	0
T9	1849	0	0	0
T10	102253	200	0	0
T11	0	12	0	0
T13	0	2	0	0
T14	0	4	0	0
T23	0	110	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12537271	1310	0	0
T4	6607	8	0	0
T5	5101	0	0	0
T6	1918	0	0	0
T7	3413	0	0	0
T8	39911	5	0	0
T9	1849	0	0	0
T10	102253	23	0	0
T11	3909	0	0	0
T12	3692	0	0	0
T13	1748	0	0	0
T23	0	6	0	0
T24	0	32	0	0
T50	0	23	0	0
T52	0	1	0	0
T53	0	19	0	0
T61	0	10	0	0
T68	0	1	0	0