Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11798833	8659	0	0
alert_regwen_rd_A	11798833	3510	0	0
cpu_regwen_rd_A	11798833	3469	0	0
sw_rst_ctrl_n_0_rd_A	11798833	8839	0	0
sw_rst_ctrl_n_1_rd_A	11798833	9010	0	0
sw_rst_ctrl_n_2_rd_A	11798833	8831	0	0
sw_rst_ctrl_n_3_rd_A	11798833	8896	0	0
sw_rst_ctrl_n_4_rd_A	11798833	9094	0	0
sw_rst_ctrl_n_5_rd_A	11798833	8957	0	0
sw_rst_ctrl_n_6_rd_A	11798833	8937	0	0
sw_rst_ctrl_n_7_rd_A	11798833	9305	0	0
sw_rst_regwen_0_rd_A	11798833	4108	0	0
sw_rst_regwen_1_rd_A	11798833	4258	0	0
sw_rst_regwen_2_rd_A	11798833	4174	0	0
sw_rst_regwen_3_rd_A	11798833	4119	0	0
sw_rst_regwen_4_rd_A	11798833	4019	0	0
sw_rst_regwen_5_rd_A	11798833	4120	0	0
sw_rst_regwen_6_rd_A	11798833	4324	0	0
sw_rst_regwen_7_rd_A	11798833	4228	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	8659	0	0
T66	11785	4	0	0
T69	6049	510	0	0
T70	4817	34	0	0
T71	4682	549	0	0
T72	9588	4	0	0
T81	4569	19	0	0
T82	3715	201	0	0
T83	3563	70	0	0
T84	2473	5	0	0
T85	2676	7	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	3510	0	0
T15	5418	0	0	0
T23	116964	104	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T50	57488	0	0	0
T52	0	183	0	0
T54	0	161	0	0
T61	2933	0	0	0
T68	5647	0	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	62	0	0
T90	0	41	0	0
T91	0	75	0	0
T92	0	15	0	0
T114	0	62	0	0
T115	0	26	0	0
T116	0	63	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	3469	0	0
T15	5418	0	0	0
T23	116964	122	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T50	57488	0	0	0
T52	0	158	0	0
T54	0	203	0	0
T61	2933	0	0	0
T68	5647	0	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	82	0	0
T90	0	26	0	0
T91	0	51	0	0
T92	0	32	0	0
T114	0	76	0	0
T115	0	37	0	0
T116	0	58	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	8839	0	0
T14	5718	17	0	0
T15	5418	0	0	0
T23	116964	191	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	173	0	0
T54	0	378	0	0
T61	2933	0	0	0
T62	0	111	0	0
T68	5647	20	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	567	0	0
T117	0	204	0	0
T118	0	16	0	0
T119	0	13	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	9010	0	0
T14	5718	17	0	0
T15	5418	0	0	0
T23	116964	234	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	187	0	0
T54	0	421	0	0
T61	2933	0	0	0
T62	0	122	0	0
T68	5647	21	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	535	0	0
T117	0	210	0	0
T118	0	20	0	0
T119	0	24	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	8831	0	0
T14	5718	17	0	0
T15	5418	0	0	0
T23	116964	242	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	202	0	0
T54	0	391	0	0
T61	2933	0	0	0
T62	0	77	0	0
T68	5647	12	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	570	0	0
T117	0	193	0	0
T118	0	7	0	0
T119	0	19	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	8896	0	0
T14	5718	12	0	0
T15	5418	0	0	0
T23	116964	211	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	178	0	0
T54	0	413	0	0
T61	2933	0	0	0
T62	0	86	0	0
T68	5647	11	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	541	0	0
T117	0	207	0	0
T118	0	17	0	0
T119	0	28	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	9094	0	0
T14	5718	14	0	0
T15	5418	0	0	0
T23	116964	185	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	217	0	0
T54	0	367	0	0
T61	2933	0	0	0
T62	0	109	0	0
T68	5647	11	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	599	0	0
T117	0	181	0	0
T118	0	8	0	0
T119	0	20	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	8957	0	0
T14	5718	2	0	0
T15	5418	0	0	0
T23	116964	206	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	161	0	0
T54	0	333	0	0
T61	2933	0	0	0
T62	0	119	0	0
T68	5647	19	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	580	0	0
T117	0	207	0	0
T118	0	15	0	0
T119	0	15	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	8937	0	0
T14	5718	16	0	0
T15	5418	0	0	0
T23	116964	221	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	195	0	0
T54	0	401	0	0
T61	2933	0	0	0
T62	0	119	0	0
T68	5647	23	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	565	0	0
T117	0	208	0	0
T118	0	15	0	0
T119	0	30	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	9305	0	0
T14	5718	17	0	0
T15	5418	0	0	0
T23	116964	190	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T52	0	208	0	0
T54	0	397	0	0
T61	2933	0	0	0
T62	0	118	0	0
T68	5647	21	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	589	0	0
T117	0	235	0	0
T118	0	18	0	0
T119	0	15	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4108	0	0
T14	5718	13	0	0
T15	5418	0	0	0
T23	116964	121	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	24	0	0
T52	0	173	0	0
T54	0	246	0	0
T61	2933	0	0	0
T62	0	20	0	0
T68	5647	6	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	66	0	0
T117	0	26	0	0
T118	0	1	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4258	0	0
T14	5718	4	0	0
T15	5418	0	0	0
T23	116964	85	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	40	0	0
T52	0	158	0	0
T54	0	227	0	0
T61	2933	0	0	0
T62	0	33	0	0
T68	5647	3	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	52	0	0
T117	0	13	0	0
T118	0	11	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4174	0	0
T14	5718	6	0	0
T15	5418	0	0	0
T23	116964	111	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	28	0	0
T52	0	155	0	0
T54	0	271	0	0
T61	2933	0	0	0
T62	0	30	0	0
T68	5647	7	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	80	0	0
T117	0	49	0	0
T118	0	3	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4119	0	0
T14	5718	8	0	0
T15	5418	0	0	0
T23	116964	90	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	21	0	0
T52	0	216	0	0
T54	0	228	0	0
T61	2933	0	0	0
T62	0	15	0	0
T68	5647	12	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	77	0	0
T117	0	22	0	0
T118	0	11	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4019	0	0
T14	5718	5	0	0
T15	5418	0	0	0
T23	116964	119	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	23	0	0
T52	0	186	0	0
T54	0	222	0	0
T61	2933	0	0	0
T62	0	22	0	0
T68	5647	10	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	45	0	0
T117	0	33	0	0
T118	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4120	0	0
T14	5718	6	0	0
T15	5418	0	0	0
T23	116964	98	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	43	0	0
T52	0	152	0	0
T54	0	174	0	0
T61	2933	0	0	0
T62	0	22	0	0
T68	5647	2	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	66	0	0
T117	0	25	0	0
T118	0	2	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4324	0	0
T14	5718	12	0	0
T15	5418	0	0	0
T23	116964	122	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	16	0	0
T52	0	175	0	0
T54	0	227	0	0
T61	2933	0	0	0
T62	0	12	0	0
T68	5647	4	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	61	0	0
T117	0	21	0	0
T118	0	7	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11798833	4228	0	0
T14	5718	1	0	0
T15	5418	0	0	0
T23	116964	139	0	0
T24	84231	0	0	0
T25	5316	0	0	0
T38	0	29	0	0
T52	0	197	0	0
T54	0	261	0	0
T61	2933	0	0	0
T62	0	20	0	0
T68	5647	7	0	0
T73	5113	0	0	0
T79	3248	0	0	0
T80	5110	0	0	0
T88	0	59	0	0
T117	0	22	0	0
T118	0	8	0	0