Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	588410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

355418

1

T3

72

T5

1117

T6

6028

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	502413	1			T1	1		T3	99		T5	1605
values[0x0]	220699	1			T3	60		T5	651		T6	3612
values[0x1]	220716	1			T3	53		T5	596		T6	3566

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	493858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

449970

1

T1

1

T3

91

T5

1380

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3504	1			T3	2		T5	17		T6	39
valid_sources[0x01]	4232	1			T5	16		T6	44		T7	3
valid_sources[0x02]	3521	1			T5	15		T6	34		T8	1
valid_sources[0x03]	3292	1			T5	29		T6	99		T7	1
valid_sources[0x04]	4047	1			T5	13		T6	84		T8	1
valid_sources[0x05]	2846	1			T3	1		T5	11		T6	36
valid_sources[0x06]	6968	1			T5	14		T6	113		T8	2
valid_sources[0x07]	4428	1			T5	15		T6	45		T8	12
valid_sources[0x08]	3744	1			T5	13		T6	77		T8	4
valid_sources[0x09]	3730	1			T5	11		T6	47		T11	39
valid_sources[0x0a]	3134	1			T5	4		T6	50		T11	78
valid_sources[0x0b]	5945	1			T3	1		T5	25		T6	56
valid_sources[0x0c]	3821	1			T5	2		T6	57		T8	1
valid_sources[0x0d]	3216	1			T3	2		T5	2		T6	58
valid_sources[0x0e]	3616	1			T5	4		T6	61		T11	38
valid_sources[0x0f]	3222	1			T5	11		T6	67		T7	5
valid_sources[0x10]	2966	1			T5	15		T6	75		T8	8
valid_sources[0x11]	4478	1			T5	13		T6	65		T8	4
valid_sources[0x12]	3298	1			T5	5		T6	45		T9	3
valid_sources[0x13]	3797	1			T5	8		T6	60		T7	6
valid_sources[0x14]	3485	1			T3	1		T5	14		T6	59
valid_sources[0x15]	3215	1			T5	4		T6	75		T8	3
valid_sources[0x16]	3733	1			T3	5		T5	8		T6	66
valid_sources[0x17]	3400	1			T5	2		T6	97		T7	4
valid_sources[0x18]	3893	1			T3	3		T5	2		T6	67
valid_sources[0x19]	3646	1			T5	9		T6	47		T7	3
valid_sources[0x1a]	3101	1			T5	7		T6	47		T8	1
valid_sources[0x1b]	3221	1			T5	12		T6	64		T11	63
valid_sources[0x1c]	3091	1			T5	12		T6	73		T11	64
valid_sources[0x1d]	3944	1			T3	3		T5	4		T6	49
valid_sources[0x1e]	3621	1			T5	3		T6	37		T7	1
valid_sources[0x1f]	4521	1			T5	11		T6	56		T8	2
valid_sources[0x20]	3101	1			T5	10		T6	67		T7	1
valid_sources[0x21]	3979	1			T5	16		T6	104		T10	6
valid_sources[0x22]	3271	1			T3	1		T5	13		T6	76
valid_sources[0x23]	3214	1			T5	8		T6	40		T7	4
valid_sources[0x24]	3843	1			T3	2		T5	6		T6	109
valid_sources[0x25]	4856	1			T3	2		T5	7		T6	63
valid_sources[0x26]	3712	1			T5	22		T6	56		T8	2
valid_sources[0x27]	4085	1			T5	6		T6	57		T8	6
valid_sources[0x28]	3458	1			T5	6		T6	57		T10	1
valid_sources[0x29]	3627	1			T3	1		T5	15		T6	84
valid_sources[0x2a]	3807	1			T3	3		T5	12		T6	85
valid_sources[0x2b]	3253	1			T5	3		T6	111		T7	6
valid_sources[0x2c]	3748	1			T5	13		T6	43		T8	6
valid_sources[0x2d]	3059	1			T5	10		T6	57		T8	4
valid_sources[0x2e]	2992	1			T5	5		T6	27		T8	1
valid_sources[0x2f]	4003	1			T5	14		T6	69		T10	8
valid_sources[0x30]	3371	1			T5	12		T6	54		T7	1
valid_sources[0x31]	2928	1			T5	6		T6	59		T7	8
valid_sources[0x32]	3878	1			T3	2		T5	12		T6	63
valid_sources[0x33]	3100	1			T5	16		T6	51		T7	5
valid_sources[0x34]	3381	1			T3	1		T5	10		T6	90
valid_sources[0x35]	3361	1			T5	10		T6	88		T7	2
valid_sources[0x36]	3991	1			T3	2		T5	12		T6	53
valid_sources[0x37]	2961	1			T3	2		T5	5		T6	54
valid_sources[0x38]	3146	1			T5	3		T6	53		T11	50
valid_sources[0x39]	3755	1			T5	10		T6	62		T7	2
valid_sources[0x3a]	3457	1			T5	9		T6	62		T11	43
valid_sources[0x3b]	2909	1			T5	31		T6	122		T8	2
valid_sources[0x3c]	3632	1			T5	11		T6	100		T11	59
valid_sources[0x3d]	3252	1			T5	12		T6	55		T8	3
valid_sources[0x3e]	3366	1			T5	15		T6	58		T8	3
valid_sources[0x3f]	4677	1			T5	17		T6	42		T7	5
valid_sources[0x40]	5886	1			T5	7		T6	43		T10	6
valid_sources[0x41]	3034	1			T5	9		T6	76		T11	37
valid_sources[0x42]	3108	1			T5	16		T6	43		T7	14
valid_sources[0x43]	2846	1			T5	20		T6	71		T8	4
valid_sources[0x44]	3147	1			T5	14		T6	56		T10	8
valid_sources[0x45]	4070	1			T5	21		T6	75		T8	4
valid_sources[0x46]	3474	1			T3	2		T5	7		T6	50
valid_sources[0x47]	3488	1			T3	1		T5	9		T6	105
valid_sources[0x48]	2879	1			T5	17		T6	52		T10	2
valid_sources[0x49]	3343	1			T5	10		T6	62		T10	3
valid_sources[0x4a]	3224	1			T5	13		T6	51		T7	2
valid_sources[0x4b]	4917	1			T5	6		T6	103		T10	15
valid_sources[0x4c]	3178	1			T5	11		T6	37		T8	6
valid_sources[0x4d]	4130	1			T3	3		T5	15		T6	58
valid_sources[0x4e]	3197	1			T5	20		T6	34		T7	4
valid_sources[0x4f]	6271	1			T5	4		T6	54		T7	11
valid_sources[0x50]	3274	1			T5	13		T6	75		T11	47
valid_sources[0x51]	3619	1			T3	3		T5	8		T6	42
valid_sources[0x52]	3907	1			T5	23		T6	62		T11	43
valid_sources[0x53]	7052	1			T3	2		T5	11		T6	95
valid_sources[0x54]	3319	1			T5	4		T6	83		T11	59
valid_sources[0x55]	4506	1			T3	3		T5	12		T6	82
valid_sources[0x56]	2988	1			T5	12		T6	34		T7	1
valid_sources[0x57]	3466	1			T3	1		T5	10		T6	49
valid_sources[0x58]	3004	1			T5	3		T6	104		T8	3
valid_sources[0x59]	3434	1			T3	3		T5	11		T6	76
valid_sources[0x5a]	3432	1			T5	8		T6	97		T10	25
valid_sources[0x5b]	2969	1			T3	5		T5	8		T6	67
valid_sources[0x5c]	4188	1			T3	6		T5	10		T6	77
valid_sources[0x5d]	3539	1			T5	6		T6	52		T7	2
valid_sources[0x5e]	3129	1			T5	19		T6	50		T8	2
valid_sources[0x5f]	3271	1			T5	8		T6	48		T8	7
valid_sources[0x60]	3690	1			T5	9		T6	50		T10	2
valid_sources[0x61]	2849	1			T3	5		T5	10		T6	88
valid_sources[0x62]	3439	1			T6	52		T7	1		T10	7
valid_sources[0x63]	4218	1			T5	12		T6	50		T10	18
valid_sources[0x64]	3343	1			T3	5		T5	6		T6	75
valid_sources[0x65]	6077	1			T5	12		T6	76		T7	1
valid_sources[0x66]	3184	1			T5	4		T6	78		T10	2
valid_sources[0x67]	3536	1			T3	2		T5	5		T6	69
valid_sources[0x68]	3203	1			T3	1		T5	1		T6	71
valid_sources[0x69]	3930	1			T3	7		T5	7		T6	58
valid_sources[0x6a]	3722	1			T5	3		T6	40		T7	12
valid_sources[0x6b]	3513	1			T5	16		T6	76		T7	1
valid_sources[0x6c]	3734	1			T3	2		T5	12		T6	63
valid_sources[0x6d]	4175	1			T5	3		T6	95		T11	37
valid_sources[0x6e]	2682	1			T5	4		T6	65		T8	1
valid_sources[0x6f]	6486	1			T3	5		T5	27		T6	33
valid_sources[0x70]	3952	1			T5	15		T6	83		T10	10
valid_sources[0x71]	2823	1			T5	1		T6	48		T11	40
valid_sources[0x72]	3618	1			T3	3		T5	10		T6	60
valid_sources[0x73]	4199	1			T3	1		T5	6		T6	86
valid_sources[0x74]	2811	1			T3	3		T5	4		T6	47
valid_sources[0x75]	3325	1			T3	5		T5	3		T6	62
valid_sources[0x76]	2813	1			T3	3		T5	5		T6	96
valid_sources[0x77]	3191	1			T3	3		T5	6		T6	63
valid_sources[0x78]	3586	1			T5	7		T6	65		T10	9
valid_sources[0x79]	3122	1			T5	9		T6	34		T10	6
valid_sources[0x7a]	4634	1			T5	21		T6	43		T10	1
valid_sources[0x7b]	6737	1			T5	11		T6	51		T8	1
valid_sources[0x7c]	3039	1			T3	2		T5	4		T6	29
valid_sources[0x7d]	3090	1			T5	14		T6	40		T10	26
valid_sources[0x7e]	3543	1			T3	1		T5	19		T6	51
valid_sources[0x7f]	3960	1			T5	9		T6	31		T10	4
valid_sources[0x80]	3268	1			T5	21		T6	98		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

236152

1

T3

43

T5

777

T6

4243

values[0x0]

all_enables

biggest_size

77663

1

T3

23

T5

234

T6

1205

values[0x1]

all_enables

biggest_size

41603

1

T3

6

T5

106

T6

580