Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10897198	12749	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10897198	117715	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10897198	6053761	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10897198	187725	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10897198	12749	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10897198	117715	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10897198	6053761	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10897198	187725	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	12749	0	0
T3	3264	4	0	0
T4	5078	0	0	0
T5	41422	36	0	0
T6	99461	183	0	0
T7	3989	4	0	0
T8	4469	4	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	146	0	0
T12	110795	227	0	0
T14	0	4	0	0
T23	0	4	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	117715	0	0
T3	3264	38	0	0
T4	5078	0	0	0
T5	41422	333	0	0
T6	99461	1675	0	0
T7	3989	37	0	0
T8	4469	38	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	1334	0	0
T12	110795	2063	0	0
T14	0	37	0	0
T23	0	37	0	0
T24	0	37	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	6053761	0	0
T1	2738	772	0	0
T2	5490	572	0	0
T3	3264	2313	0	0
T4	5078	575	0	0
T5	41422	31314	0	0
T6	99461	49502	0	0
T7	3989	3003	0	0
T8	4469	3501	0	0
T9	1914	1269	0	0
T10	8725	8123	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	187725	0	0
T3	3264	69	0	0
T4	5078	0	0	0
T5	41422	528	0	0
T6	99461	2702	0	0
T7	3989	64	0	0
T8	4469	67	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	2158	0	0
T12	110795	3325	0	0
T14	0	58	0	0
T23	0	61	0	0
T24	0	57	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	12749	0	0
T3	3264	4	0	0
T4	5078	0	0	0
T5	41422	36	0	0
T6	99461	183	0	0
T7	3989	4	0	0
T8	4469	4	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	146	0	0
T12	110795	227	0	0
T14	0	4	0	0
T23	0	4	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	117715	0	0
T3	3264	38	0	0
T4	5078	0	0	0
T5	41422	333	0	0
T6	99461	1675	0	0
T7	3989	37	0	0
T8	4469	38	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	1334	0	0
T12	110795	2063	0	0
T14	0	37	0	0
T23	0	37	0	0
T24	0	37	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	6053761	0	0
T1	2738	772	0	0
T2	5490	572	0	0
T3	3264	2313	0	0
T4	5078	575	0	0
T5	41422	31314	0	0
T6	99461	49502	0	0
T7	3989	3003	0	0
T8	4469	3501	0	0
T9	1914	1269	0	0
T10	8725	8123	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	187725	0	0
T3	3264	69	0	0
T4	5078	0	0	0
T5	41422	528	0	0
T6	99461	2702	0	0
T7	3989	64	0	0
T8	4469	67	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	2158	0	0
T12	110795	3325	0	0
T14	0	58	0	0
T23	0	61	0	0
T24	0	57	0	0