Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51626400	8929	0	0
CascadeEffAonToRstPorAboveRise_A	51626400	8929	0	0
CascadeEffAonToRstPorIoAboveFall_A	49559315	8929	0	0
CascadeEffAonToRstPorIoAboveRise_A	49559315	8929	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24780602	8929	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24780602	8929	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12389955	8929	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12389955	8929	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24780521	8929	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24780521	8929	0	0
CascadeLcToLcAboveFall_A	51626400	21678	0	0
CascadeLcToLcAboveRise_A	51626400	21678	0	0
CascadeLcToLcAonAboveFall_A	1563959	21678	0	0
CascadeLcToLcAonAboveRise_A	1563959	21678	0	0
CascadeLcToLcShadowedAboveFall_A	51626400	21678	0	0
CascadeLcToLcShadowedAboveRise_A	51626400	21678	0	0
CascadePorToAonAboveFall_A	1563959	7261	0	0
CascadeSysToSysAboveFall_A	51626400	21678	0	0
CascadeSysToSysAboveRise_A	51626400	21678	0	0
ScanRstToAonRise_A	1563959	208	0	0
StablePorToAonRise_A	1563959	8929	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10897198	21678	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10897198	21678	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10897198	21678	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10897198	21678	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12389955	21678	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12389955	21678	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10897198	21678	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10897198	21678	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10897198	21678	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10897198	21678	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	8929	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	2	0	0
T4	24231	8	0	0
T5	192116	20	0	0
T6	516147	109	0	0
T7	17230	2	0	0
T8	19811	2	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	8929	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	2	0	0
T4	24231	8	0	0
T5	192116	20	0	0
T6	516147	109	0	0
T7	17230	2	0	0
T8	19811	2	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49559315	8929	0	0
T1	11413	2	0	0
T2	23375	8	0	0
T3	14410	2	0	0
T4	23245	8	0	0
T5	184432	20	0	0
T6	495434	109	0	0
T7	16541	2	0	0
T8	19010	2	0	0
T9	7733	1	0	0
T10	35171	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49559315	8929	0	0
T1	11413	2	0	0
T2	23375	8	0	0
T3	14410	2	0	0
T4	23245	8	0	0
T5	184432	20	0	0
T6	495434	109	0	0
T7	16541	2	0	0
T8	19010	2	0	0
T9	7733	1	0	0
T10	35171	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780602	8929	0	0
T1	5706	2	0	0
T2	11679	8	0	0
T3	7205	2	0	0
T4	11631	8	0	0
T5	92231	20	0	0
T6	247764	109	0	0
T7	8267	2	0	0
T8	9507	2	0	0
T9	3867	1	0	0
T10	17585	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780602	8929	0	0
T1	5706	2	0	0
T2	11679	8	0	0
T3	7205	2	0	0
T4	11631	8	0	0
T5	92231	20	0	0
T6	247764	109	0	0
T7	8267	2	0	0
T8	9507	2	0	0
T9	3867	1	0	0
T10	17585	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	8929	0	0
T1	2852	2	0	0
T2	5844	8	0	0
T3	3602	2	0	0
T4	5816	8	0	0
T5	46105	20	0	0
T6	123874	109	0	0
T7	4135	2	0	0
T8	4752	2	0	0
T9	1933	1	0	0
T10	8791	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	8929	0	0
T1	2852	2	0	0
T2	5844	8	0	0
T3	3602	2	0	0
T4	5816	8	0	0
T5	46105	20	0	0
T6	123874	109	0	0
T7	4135	2	0	0
T8	4752	2	0	0
T9	1933	1	0	0
T10	8791	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780521	8929	0	0
T1	5706	2	0	0
T2	11688	8	0	0
T3	7204	2	0	0
T4	11627	8	0	0
T5	92223	20	0	0
T6	247745	109	0	0
T7	8270	2	0	0
T8	9508	2	0	0
T9	3866	1	0	0
T10	17585	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780521	8929	0	0
T1	5706	2	0	0
T2	11688	8	0	0
T3	7204	2	0	0
T4	11627	8	0	0
T5	92223	20	0	0
T6	247745	109	0	0
T7	8270	2	0	0
T8	9508	2	0	0
T9	3866	1	0	0
T10	17585	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	21678	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	6	0	0
T4	24231	8	0	0
T5	192116	56	0	0
T6	516147	292	0	0
T7	17230	6	0	0
T8	19811	6	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	21678	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	6	0	0
T4	24231	8	0	0
T5	192116	56	0	0
T6	516147	292	0	0
T7	17230	6	0	0
T8	19811	6	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	21678	0	0
T1	355	2	0	0
T2	732	8	0	0
T3	448	6	0	0
T4	729	8	0	0
T5	5841	56	0	0
T6	15846	292	0	0
T7	516	6	0	0
T8	592	6	0	0
T9	240	1	0	0
T10	1097	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	21678	0	0
T1	355	2	0	0
T2	732	8	0	0
T3	448	6	0	0
T4	729	8	0	0
T5	5841	56	0	0
T6	15846	292	0	0
T7	516	6	0	0
T8	592	6	0	0
T9	240	1	0	0
T10	1097	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	21678	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	6	0	0
T4	24231	8	0	0
T5	192116	56	0	0
T6	516147	292	0	0
T7	17230	6	0	0
T8	19811	6	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	21678	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	6	0	0
T4	24231	8	0	0
T5	192116	56	0	0
T6	516147	292	0	0
T7	17230	6	0	0
T8	19811	6	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	7261	0	0
T1	355	8	0	0
T2	732	8	0	0
T3	448	1	0	0
T4	729	8	0	0
T5	5841	13	0	0
T6	15846	57	0	0
T7	516	1	0	0
T8	592	1	0	0
T9	240	1	0	0
T10	1097	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	21678	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	6	0	0
T4	24231	8	0	0
T5	192116	56	0	0
T6	516147	292	0	0
T7	17230	6	0	0
T8	19811	6	0	0
T9	8055	1	0	0
T10	36636	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51626400	21678	0	0
T1	11889	2	0	0
T2	24344	8	0	0
T3	15013	6	0	0
T4	24231	8	0	0
T5	192116	56	0	0
T6	516147	292	0	0
T7	17230	6	0	0
T8	19811	6	0	0
T9	8055	1	0	0
T10	36636	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	208	0	0
T6	15846	8	0	0
T7	516	0	0	0
T8	592	0	0	0
T9	240	0	0	0
T10	1097	0	0	0
T11	20206	3	0	0
T12	18050	6	0	0
T13	437	0	0	0
T14	303	0	0	0
T23	452	0	0	0
T40	0	1	0	0
T63	0	6	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0
T97	0	4	0	0
T103	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	8929	0	0
T1	355	2	0	0
T2	732	8	0	0
T3	448	2	0	0
T4	729	8	0	0
T5	5841	20	0	0
T6	15846	109	0	0
T7	516	2	0	0
T8	592	2	0	0
T9	240	1	0	0
T10	1097	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	21678	0	0
T1	2852	2	0	0
T2	5844	8	0	0
T3	3602	6	0	0
T4	5816	8	0	0
T5	46105	56	0	0
T6	123874	292	0	0
T7	4135	6	0	0
T8	4752	6	0	0
T9	1933	1	0	0
T10	8791	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	21678	0	0
T1	2852	2	0	0
T2	5844	8	0	0
T3	3602	6	0	0
T4	5816	8	0	0
T5	46105	56	0	0
T6	123874	292	0	0
T7	4135	6	0	0
T8	4752	6	0	0
T9	1933	1	0	0
T10	8791	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10897198	21678	0	0
T1	2738	2	0	0
T2	5490	8	0	0
T3	3264	6	0	0
T4	5078	8	0	0
T5	41422	56	0	0
T6	99461	292	0	0
T7	3989	6	0	0
T8	4469	6	0	0
T9	1914	1	0	0
T10	8725	1	0	0