Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12389955	13469	0	0
gen_assertions[0].RstEnOn_A	12389955	938	0	0
gen_assertions[0].RstNOff_A	12389955	13469	0	0
gen_assertions[0].RstNOn_A	12389955	938	0	0
gen_assertions[1].RstEnOff_A	49559315	12270	0	0
gen_assertions[1].RstEnOn_A	49559315	876	0	0
gen_assertions[1].RstNOff_A	49559315	12270	0	0
gen_assertions[1].RstNOn_A	49559315	876	0	0
gen_assertions[2].RstEnOff_A	24780602	12331	0	0
gen_assertions[2].RstEnOn_A	24780602	870	0	0
gen_assertions[2].RstNOff_A	24780602	12331	0	0
gen_assertions[2].RstNOn_A	24780602	870	0	0
gen_assertions[3].RstEnOff_A	24780521	12380	0	0
gen_assertions[3].RstEnOn_A	24780521	907	0	0
gen_assertions[3].RstNOff_A	24780521	12380	0	0
gen_assertions[3].RstNOn_A	24780521	907	0	0
gen_assertions[4].RstEnOff_A	1563959	21277	0	0
gen_assertions[4].RstEnOn_A	1563959	963	0	0
gen_assertions[4].RstNOff_A	1563959	21277	0	0
gen_assertions[4].RstNOn_A	1563959	963	0	0
gen_assertions[5].RstEnOff_A	12389955	13738	0	0
gen_assertions[5].RstEnOn_A	12389955	1020	0	0
gen_assertions[5].RstNOff_A	12389955	13738	0	0
gen_assertions[5].RstNOn_A	12389955	1020	0	0
gen_assertions[6].RstEnOff_A	12389955	13783	0	0
gen_assertions[6].RstEnOn_A	12389955	1067	0	0
gen_assertions[6].RstNOff_A	12389955	13783	0	0
gen_assertions[6].RstNOn_A	12389955	1067	0	0
gen_assertions[7].RstEnOff_A	12389955	13813	0	0
gen_assertions[7].RstEnOn_A	12389955	1096	0	0
gen_assertions[7].RstNOff_A	12389955	13813	0	0
gen_assertions[7].RstNOn_A	12389955	1096	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13469	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	207	0	0
T7	4135	4	0	0
T8	4752	5	0	0
T9	1933	0	0	0
T10	8791	5	0	0
T11	159546	156	0	0
T12	140728	247	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	938	0	0
T6	123874	26	0	0
T7	4135	0	0	0
T8	4752	1	0	0
T9	1933	0	0	0
T10	8791	5	0	0
T11	159546	11	0	0
T12	140728	21	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T46	0	4	0	0
T53	0	6	0	0
T63	0	5	0	0
T82	0	3	0	0
T83	0	12	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13469	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	207	0	0
T7	4135	4	0	0
T8	4752	5	0	0
T9	1933	0	0	0
T10	8791	5	0	0
T11	159546	156	0	0
T12	140728	247	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	938	0	0
T6	123874	26	0	0
T7	4135	0	0	0
T8	4752	1	0	0
T9	1933	0	0	0
T10	8791	5	0	0
T11	159546	11	0	0
T12	140728	21	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T46	0	4	0	0
T53	0	6	0	0
T63	0	5	0	0
T82	0	3	0	0
T83	0	12	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49559315	12270	0	0
T3	14410	4	0	0
T4	23245	0	0	0
T5	184432	29	0	0
T6	495434	181	0	0
T7	16541	4	0	0
T8	19010	4	0	0
T9	7733	0	0	0
T10	35171	6	0	0
T11	638169	151	0	0
T12	562892	225	0	0
T14	0	2	0	0
T23	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49559315	876	0	0
T6	495434	21	0	0
T7	16541	0	0	0
T8	19010	0	0	0
T9	7733	0	0	0
T10	35171	6	0	0
T11	638169	18	0	0
T12	562892	25	0	0
T13	14036	0	0	0
T14	9715	0	0	0
T23	14471	0	0	0
T46	0	6	0	0
T53	0	7	0	0
T63	0	5	0	0
T82	0	2	0	0
T83	0	6	0	0
T84	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49559315	12270	0	0
T3	14410	4	0	0
T4	23245	0	0	0
T5	184432	29	0	0
T6	495434	181	0	0
T7	16541	4	0	0
T8	19010	4	0	0
T9	7733	0	0	0
T10	35171	6	0	0
T11	638169	151	0	0
T12	562892	225	0	0
T14	0	2	0	0
T23	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49559315	876	0	0
T6	495434	21	0	0
T7	16541	0	0	0
T8	19010	0	0	0
T9	7733	0	0	0
T10	35171	6	0	0
T11	638169	18	0	0
T12	562892	25	0	0
T13	14036	0	0	0
T14	9715	0	0	0
T23	14471	0	0	0
T46	0	6	0	0
T53	0	7	0	0
T63	0	5	0	0
T82	0	2	0	0
T83	0	6	0	0
T84	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780602	12331	0	0
T3	7205	4	0	0
T4	11631	0	0	0
T5	92231	29	0	0
T6	247764	186	0	0
T7	8267	4	0	0
T8	9507	4	0	0
T9	3867	0	0	0
T10	17585	8	0	0
T11	319084	148	0	0
T12	281446	223	0	0
T14	0	2	0	0
T23	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780602	870	0	0
T6	247764	25	0	0
T7	8267	0	0	0
T8	9507	0	0	0
T9	3867	0	0	0
T10	17585	8	0	0
T11	319084	14	0	0
T12	281446	23	0	0
T13	7018	0	0	0
T14	4860	0	0	0
T23	7235	0	0	0
T36	0	9	0	0
T46	0	5	0	0
T53	0	9	0	0
T63	0	5	0	0
T82	0	4	0	0
T84	0	2	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780602	12331	0	0
T3	7205	4	0	0
T4	11631	0	0	0
T5	92231	29	0	0
T6	247764	186	0	0
T7	8267	4	0	0
T8	9507	4	0	0
T9	3867	0	0	0
T10	17585	8	0	0
T11	319084	148	0	0
T12	281446	223	0	0
T14	0	2	0	0
T23	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780602	870	0	0
T6	247764	25	0	0
T7	8267	0	0	0
T8	9507	0	0	0
T9	3867	0	0	0
T10	17585	8	0	0
T11	319084	14	0	0
T12	281446	23	0	0
T13	7018	0	0	0
T14	4860	0	0	0
T23	7235	0	0	0
T36	0	9	0	0
T46	0	5	0	0
T53	0	9	0	0
T63	0	5	0	0
T82	0	4	0	0
T84	0	2	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780521	12380	0	0
T3	7204	4	0	0
T4	11627	0	0	0
T5	92223	29	0	0
T6	247745	182	0	0
T7	8270	4	0	0
T8	9508	4	0	0
T9	3866	0	0	0
T10	17585	6	0	0
T11	319081	149	0	0
T12	281444	221	0	0
T14	0	2	0	0
T23	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780521	907	0	0
T6	247745	22	0	0
T7	8270	0	0	0
T8	9508	0	0	0
T9	3866	0	0	0
T10	17585	6	0	0
T11	319081	16	0	0
T12	281444	22	0	0
T13	7018	0	0	0
T14	4859	0	0	0
T23	7235	0	0	0
T36	0	7	0	0
T46	0	7	0	0
T53	0	11	0	0
T63	0	5	0	0
T82	0	5	0	0
T84	0	3	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780521	12380	0	0
T3	7204	4	0	0
T4	11627	0	0	0
T5	92223	29	0	0
T6	247745	182	0	0
T7	8270	4	0	0
T8	9508	4	0	0
T9	3866	0	0	0
T10	17585	6	0	0
T11	319081	149	0	0
T12	281444	221	0	0
T14	0	2	0	0
T23	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24780521	907	0	0
T6	247745	22	0	0
T7	8270	0	0	0
T8	9508	0	0	0
T9	3866	0	0	0
T10	17585	6	0	0
T11	319081	16	0	0
T12	281444	22	0	0
T13	7018	0	0	0
T14	4859	0	0	0
T23	7235	0	0	0
T36	0	7	0	0
T46	0	7	0	0
T53	0	11	0	0
T63	0	5	0	0
T82	0	5	0	0
T84	0	3	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	21277	0	0
T1	355	2	0	0
T2	732	3	0	0
T3	448	6	0	0
T4	729	3	0	0
T5	5841	54	0	0
T6	15846	313	0	0
T7	516	6	0	0
T8	592	7	0	0
T9	240	1	0	0
T10	1097	11	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	963	0	0
T6	15846	27	0	0
T7	516	0	0	0
T8	592	1	0	0
T9	240	0	0	0
T10	1097	10	0	0
T11	20206	20	0	0
T12	18050	24	0	0
T13	437	0	0	0
T14	303	0	0	0
T23	452	0	0	0
T46	0	9	0	0
T53	0	10	0	0
T63	0	6	0	0
T82	0	7	0	0
T84	0	4	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	21277	0	0
T1	355	2	0	0
T2	732	3	0	0
T3	448	6	0	0
T4	729	3	0	0
T5	5841	54	0	0
T6	15846	313	0	0
T7	516	6	0	0
T8	592	7	0	0
T9	240	1	0	0
T10	1097	11	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563959	963	0	0
T6	15846	27	0	0
T7	516	0	0	0
T8	592	1	0	0
T9	240	0	0	0
T10	1097	10	0	0
T11	20206	20	0	0
T12	18050	24	0	0
T13	437	0	0	0
T14	303	0	0	0
T23	452	0	0	0
T46	0	9	0	0
T53	0	10	0	0
T63	0	6	0	0
T82	0	7	0	0
T84	0	4	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13738	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	205	0	0
T7	4135	4	0	0
T8	4752	5	0	0
T9	1933	0	0	0
T10	8791	11	0	0
T11	159546	160	0	0
T12	140728	251	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	1020	0	0
T6	123874	22	0	0
T7	4135	0	0	0
T8	4752	1	0	0
T9	1933	0	0	0
T10	8791	11	0	0
T11	159546	16	0	0
T12	140728	25	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T46	0	10	0	0
T53	0	13	0	0
T63	0	7	0	0
T82	0	7	0	0
T84	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13738	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	205	0	0
T7	4135	4	0	0
T8	4752	5	0	0
T9	1933	0	0	0
T10	8791	11	0	0
T11	159546	160	0	0
T12	140728	251	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	1020	0	0
T6	123874	22	0	0
T7	4135	0	0	0
T8	4752	1	0	0
T9	1933	0	0	0
T10	8791	11	0	0
T11	159546	16	0	0
T12	140728	25	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T46	0	10	0	0
T53	0	13	0	0
T63	0	7	0	0
T82	0	7	0	0
T84	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13783	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	209	0	0
T7	4135	4	0	0
T8	4752	5	0	0
T9	1933	0	0	0
T10	8791	14	0	0
T11	159546	160	0	0
T12	140728	249	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	1067	0	0
T6	123874	28	0	0
T7	4135	0	0	0
T8	4752	1	0	0
T9	1933	0	0	0
T10	8791	14	0	0
T11	159546	16	0	0
T12	140728	23	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T46	0	10	0	0
T53	0	11	0	0
T63	0	4	0	0
T82	0	7	0	0
T84	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13783	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	209	0	0
T7	4135	4	0	0
T8	4752	5	0	0
T9	1933	0	0	0
T10	8791	14	0	0
T11	159546	160	0	0
T12	140728	249	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	1067	0	0
T6	123874	28	0	0
T7	4135	0	0	0
T8	4752	1	0	0
T9	1933	0	0	0
T10	8791	14	0	0
T11	159546	16	0	0
T12	140728	23	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T46	0	10	0	0
T53	0	11	0	0
T63	0	4	0	0
T82	0	7	0	0
T84	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13813	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	206	0	0
T7	4135	4	0	0
T8	4752	4	0	0
T9	1933	0	0	0
T10	8791	13	0	0
T11	159546	159	0	0
T12	140728	248	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	1096	0	0
T6	123874	23	0	0
T7	4135	0	0	0
T8	4752	0	0	0
T9	1933	0	0	0
T10	8791	13	0	0
T11	159546	14	0	0
T12	140728	22	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T36	0	13	0	0
T46	0	11	0	0
T53	0	12	0	0
T63	0	5	0	0
T82	0	9	0	0
T84	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	13813	0	0
T3	3602	4	0	0
T4	5816	0	0	0
T5	46105	36	0	0
T6	123874	206	0	0
T7	4135	4	0	0
T8	4752	4	0	0
T9	1933	0	0	0
T10	8791	13	0	0
T11	159546	159	0	0
T12	140728	248	0	0
T14	0	4	0	0
T23	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12389955	1096	0	0
T6	123874	23	0	0
T7	4135	0	0	0
T8	4752	0	0	0
T9	1933	0	0	0
T10	8791	13	0	0
T11	159546	14	0	0
T12	140728	22	0	0
T13	3508	0	0	0
T14	2428	0	0	0
T23	3617	0	0	0
T36	0	13	0	0
T46	0	11	0	0
T53	0	12	0	0
T63	0	5	0	0
T82	0	9	0	0
T84	0	8	0	0