Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11662284	7907	0	0
alert_regwen_rd_A	11662284	3598	0	0
cpu_regwen_rd_A	11662284	3728	0	0
sw_rst_ctrl_n_0_rd_A	11662284	7735	0	0
sw_rst_ctrl_n_1_rd_A	11662284	8008	0	0
sw_rst_ctrl_n_2_rd_A	11662284	7661	0	0
sw_rst_ctrl_n_3_rd_A	11662284	7639	0	0
sw_rst_ctrl_n_4_rd_A	11662284	7707	0	0
sw_rst_ctrl_n_5_rd_A	11662284	8145	0	0
sw_rst_ctrl_n_6_rd_A	11662284	7668	0	0
sw_rst_ctrl_n_7_rd_A	11662284	7905	0	0
sw_rst_regwen_0_rd_A	11662284	4351	0	0
sw_rst_regwen_1_rd_A	11662284	4295	0	0
sw_rst_regwen_2_rd_A	11662284	4307	0	0
sw_rst_regwen_3_rd_A	11662284	4219	0	0
sw_rst_regwen_4_rd_A	11662284	4281	0	0
sw_rst_regwen_5_rd_A	11662284	4315	0	0
sw_rst_regwen_6_rd_A	11662284	4141	0	0
sw_rst_regwen_7_rd_A	11662284	4365	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7907	0	0
T55	4188	104	0	0
T59	2894	18	0	0
T60	8425	424	0	0
T61	13728	642	0	0
T62	2615	312	0	0
T70	2289	15	0	0
T86	19720	2	0	0
T87	2892	16	0	0
T88	2700	96	0	0
T89	2462	14	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	3598	0	0
T5	41422	59	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T63	0	181	0	0
T93	0	97	0	0
T100	0	227	0	0
T107	0	66	0	0
T125	0	96	0	0
T126	0	72	0	0
T127	0	127	0	0
T128	0	68	0	0
T129	0	81	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	3728	0	0
T5	41422	48	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T63	0	257	0	0
T93	0	90	0	0
T100	0	203	0	0
T107	0	79	0	0
T125	0	90	0	0
T126	0	48	0	0
T127	0	108	0	0
T128	0	77	0	0
T129	0	60	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7735	0	0
T5	41422	78	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	151	0	0
T46	0	173	0	0
T63	0	250	0	0
T82	0	145	0	0
T93	0	89	0	0
T130	0	67	0	0
T131	0	77	0	0
T132	0	171	0	0
T133	0	10	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	8008	0	0
T5	41422	58	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	199	0	0
T46	0	179	0	0
T63	0	281	0	0
T82	0	143	0	0
T93	0	77	0	0
T130	0	50	0	0
T131	0	73	0	0
T132	0	171	0	0
T133	0	6	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7661	0	0
T5	41422	82	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	173	0	0
T46	0	141	0	0
T63	0	220	0	0
T82	0	158	0	0
T93	0	60	0	0
T130	0	82	0	0
T131	0	81	0	0
T132	0	134	0	0
T133	0	4	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7639	0	0
T5	41422	62	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	189	0	0
T46	0	115	0	0
T63	0	242	0	0
T82	0	120	0	0
T93	0	82	0	0
T130	0	104	0	0
T131	0	61	0	0
T132	0	138	0	0
T133	0	7	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7707	0	0
T5	41422	49	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	232	0	0
T46	0	178	0	0
T63	0	249	0	0
T82	0	142	0	0
T93	0	78	0	0
T130	0	93	0	0
T131	0	51	0	0
T132	0	141	0	0
T133	0	8	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	8145	0	0
T5	41422	74	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	202	0	0
T46	0	163	0	0
T63	0	267	0	0
T82	0	157	0	0
T93	0	92	0	0
T130	0	86	0	0
T131	0	73	0	0
T132	0	130	0	0
T133	0	14	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7668	0	0
T5	41422	49	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	146	0	0
T46	0	169	0	0
T63	0	254	0	0
T82	0	102	0	0
T93	0	79	0	0
T130	0	106	0	0
T131	0	69	0	0
T132	0	114	0	0
T133	0	2	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	7905	0	0
T5	41422	71	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	164	0	0
T46	0	190	0	0
T63	0	307	0	0
T82	0	164	0	0
T93	0	79	0	0
T130	0	45	0	0
T131	0	55	0	0
T132	0	134	0	0
T133	0	16	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4351	0	0
T5	41422	62	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	29	0	0
T46	0	20	0	0
T63	0	232	0	0
T82	0	29	0	0
T93	0	93	0	0
T130	0	7	0	0
T131	0	11	0	0
T132	0	35	0	0
T133	0	1	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4295	0	0
T5	41422	72	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	22	0	0
T46	0	47	0	0
T63	0	223	0	0
T82	0	42	0	0
T93	0	66	0	0
T130	0	15	0	0
T131	0	42	0	0
T132	0	21	0	0
T134	0	4	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4307	0	0
T5	41422	81	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	36	0	0
T46	0	29	0	0
T63	0	239	0	0
T82	0	20	0	0
T93	0	63	0	0
T130	0	33	0	0
T131	0	10	0	0
T132	0	21	0	0
T133	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4219	0	0
T5	41422	45	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	36	0	0
T46	0	41	0	0
T63	0	237	0	0
T82	0	27	0	0
T93	0	78	0	0
T130	0	16	0	0
T131	0	20	0	0
T132	0	22	0	0
T133	0	5	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4281	0	0
T5	41422	58	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	17	0	0
T46	0	34	0	0
T63	0	237	0	0
T82	0	36	0	0
T93	0	75	0	0
T130	0	25	0	0
T131	0	24	0	0
T132	0	25	0	0
T133	0	10	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4315	0	0
T5	41422	86	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	37	0	0
T46	0	42	0	0
T63	0	175	0	0
T82	0	39	0	0
T93	0	85	0	0
T130	0	37	0	0
T131	0	25	0	0
T132	0	38	0	0
T134	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4141	0	0
T5	41422	56	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	44	0	0
T46	0	36	0	0
T63	0	174	0	0
T82	0	26	0	0
T93	0	90	0	0
T130	0	19	0	0
T131	0	24	0	0
T132	0	28	0	0
T134	0	13	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11662284	4365	0	0
T5	41422	68	0	0
T6	99461	0	0	0
T7	3989	0	0	0
T8	4469	0	0	0
T9	1914	0	0	0
T10	8725	0	0	0
T11	139812	0	0	0
T12	110795	0	0	0
T13	3417	0	0	0
T14	2287	0	0	0
T36	0	27	0	0
T46	0	33	0	0
T63	0	274	0	0
T82	0	28	0	0
T93	0	68	0	0
T130	0	11	0	0
T131	0	30	0	0
T132	0	33	0	0
T134	0	2	0	0