Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	623719	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

375712

1

T1

986

T3

68

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	533440	1			T1	1477		T3	99		T5	1500
values[0x0]	232856	1			T1	649		T3	52		T4	2
values[0x1]	233135	1			T1	694		T3	61		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	522958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

476473

1

T1

1266

T3

93

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3879	1			T1	6		T5	11		T6	151
valid_sources[0x01]	4482	1			T1	10		T6	1063		T7	2
valid_sources[0x02]	3322	1			T1	9		T5	23		T6	3
valid_sources[0x03]	3117	1			T1	13		T5	14		T7	1
valid_sources[0x04]	3935	1			T1	16		T5	38		T6	682
valid_sources[0x05]	3295	1			T1	9		T5	11		T6	99
valid_sources[0x06]	3572	1			T1	2		T5	11		T6	66
valid_sources[0x07]	3351	1			T1	2		T5	4		T6	147
valid_sources[0x08]	3082	1			T1	7		T3	1		T5	39
valid_sources[0x09]	3557	1			T5	3		T7	4		T10	226
valid_sources[0x0a]	3247	1			T1	15		T5	9		T7	5
valid_sources[0x0b]	6555	1			T1	30		T5	8		T7	6
valid_sources[0x0c]	3519	1			T1	30		T3	1		T5	3
valid_sources[0x0d]	3951	1			T1	24		T5	25		T7	1
valid_sources[0x0e]	3086	1			T1	25		T5	10		T6	2
valid_sources[0x0f]	3047	1			T1	11		T5	10		T7	4
valid_sources[0x10]	2946	1			T1	2		T3	1		T5	3
valid_sources[0x11]	3689	1			T1	13		T5	12		T6	199
valid_sources[0x12]	3964	1			T1	11		T3	1		T5	13
valid_sources[0x13]	3929	1			T1	9		T3	2		T5	15
valid_sources[0x14]	3506	1			T1	6		T3	1		T5	16
valid_sources[0x15]	3477	1			T1	10		T3	4		T5	22
valid_sources[0x16]	3627	1			T1	27		T3	3		T5	12
valid_sources[0x17]	3369	1			T1	3		T5	13		T6	3
valid_sources[0x18]	3521	1			T1	2		T5	16		T6	149
valid_sources[0x19]	3486	1			T1	11		T5	5		T7	8
valid_sources[0x1a]	3252	1			T1	11		T3	6		T5	7
valid_sources[0x1b]	3095	1			T1	4		T5	13		T6	65
valid_sources[0x1c]	3340	1			T1	3		T3	2		T5	5
valid_sources[0x1d]	3801	1			T1	3		T5	36		T7	5
valid_sources[0x1e]	4468	1			T1	28		T3	1		T5	21
valid_sources[0x1f]	3731	1			T1	35		T3	6		T5	28
valid_sources[0x20]	6831	1			T1	16		T3	1		T5	29
valid_sources[0x21]	4422	1			T3	1		T5	4		T6	66
valid_sources[0x22]	3254	1			T1	4		T3	2		T5	14
valid_sources[0x23]	3658	1			T1	11		T6	68		T7	1
valid_sources[0x24]	3761	1			T5	8		T6	312		T7	2
valid_sources[0x25]	3640	1			T1	2		T3	3		T5	26
valid_sources[0x26]	4033	1			T1	16		T5	24		T6	3
valid_sources[0x27]	4038	1			T1	6		T3	1		T5	3
valid_sources[0x28]	3361	1			T1	13		T5	22		T7	6
valid_sources[0x29]	3973	1			T1	15		T3	2		T5	8
valid_sources[0x2a]	3962	1			T1	10		T5	9		T7	11
valid_sources[0x2b]	4451	1			T1	24		T3	5		T6	433
valid_sources[0x2c]	3845	1			T1	26		T5	25		T6	5
valid_sources[0x2d]	4214	1			T1	18		T3	2		T5	21
valid_sources[0x2e]	3561	1			T1	3		T5	15		T6	11
valid_sources[0x2f]	3212	1			T1	8		T5	9		T7	4
valid_sources[0x30]	4062	1			T1	6		T6	243		T7	6
valid_sources[0x31]	4022	1			T1	1		T5	30		T7	11
valid_sources[0x32]	5977	1			T1	1		T3	6		T5	20
valid_sources[0x33]	3184	1			T5	5		T7	3		T11	6
valid_sources[0x34]	3668	1			T1	18		T5	1		T6	221
valid_sources[0x35]	3642	1			T1	8		T5	17		T6	105
valid_sources[0x36]	6782	1			T1	13		T5	5		T6	2478
valid_sources[0x37]	3420	1			T1	16		T5	10		T6	6
valid_sources[0x38]	3713	1			T1	9		T5	16		T6	13
valid_sources[0x39]	4060	1			T1	9		T5	1		T11	4
valid_sources[0x3a]	4016	1			T5	16		T6	4		T7	3
valid_sources[0x3b]	3482	1			T1	12		T3	1		T5	28
valid_sources[0x3c]	3634	1			T1	12		T3	3		T5	2
valid_sources[0x3d]	3873	1			T1	12		T5	3		T7	6
valid_sources[0x3e]	3498	1			T1	2		T3	1		T5	8
valid_sources[0x3f]	4298	1			T1	10		T5	15		T7	8
valid_sources[0x40]	4979	1			T1	14		T5	22		T6	13
valid_sources[0x41]	3319	1			T1	22		T3	2		T5	12
valid_sources[0x42]	3680	1			T1	18		T5	33		T6	20
valid_sources[0x43]	3700	1			T1	12		T5	8		T6	65
valid_sources[0x44]	7724	1			T1	5		T3	6		T5	3
valid_sources[0x45]	3401	1			T1	14		T5	10		T7	4
valid_sources[0x46]	3196	1			T1	12		T7	5		T11	4
valid_sources[0x47]	6410	1			T1	3		T5	35		T6	99
valid_sources[0x48]	3168	1			T1	3		T3	1		T5	19
valid_sources[0x49]	3334	1			T1	5		T5	16		T7	3
valid_sources[0x4a]	3586	1			T1	27		T5	6		T6	6
valid_sources[0x4b]	6621	1			T5	9		T6	70		T7	6
valid_sources[0x4c]	3247	1			T1	4		T5	1		T7	5
valid_sources[0x4d]	3320	1			T5	5		T11	2		T13	18
valid_sources[0x4e]	4873	1			T1	17		T5	9		T7	3
valid_sources[0x4f]	3295	1			T1	1		T5	7		T6	112
valid_sources[0x50]	3445	1			T1	10		T3	3		T7	6
valid_sources[0x51]	4033	1			T1	22		T6	228		T7	6
valid_sources[0x52]	3826	1			T1	15		T5	21		T7	12
valid_sources[0x53]	3874	1			T1	3		T3	3		T5	3
valid_sources[0x54]	6790	1			T1	20		T5	7		T7	3
valid_sources[0x55]	3593	1			T1	7		T5	8		T6	1
valid_sources[0x56]	3274	1			T1	13		T5	21		T6	7
valid_sources[0x57]	4182	1			T1	25		T5	47		T6	113
valid_sources[0x58]	3819	1			T1	2		T5	13		T7	1
valid_sources[0x59]	3896	1			T1	9		T3	1		T5	30
valid_sources[0x5a]	3782	1			T1	6		T5	16		T7	3
valid_sources[0x5b]	3644	1			T1	28		T3	4		T5	13
valid_sources[0x5c]	3624	1			T1	16		T5	1		T7	10
valid_sources[0x5d]	3946	1			T3	5		T5	4		T6	185
valid_sources[0x5e]	3762	1			T1	8		T5	3		T13	12
valid_sources[0x5f]	3286	1			T1	2		T5	15		T7	2
valid_sources[0x60]	5715	1			T1	18		T3	3		T5	3
valid_sources[0x61]	3084	1			T1	12		T5	10		T7	1
valid_sources[0x62]	3669	1			T1	5		T5	15		T7	4
valid_sources[0x63]	4474	1			T5	15		T6	265		T7	4
valid_sources[0x64]	5015	1			T1	11		T3	1		T6	2
valid_sources[0x65]	3887	1			T1	3		T3	3		T5	13
valid_sources[0x66]	3498	1			T1	14		T5	10		T7	7
valid_sources[0x67]	3299	1			T1	3		T5	17		T7	1
valid_sources[0x68]	3855	1			T4	1		T5	16		T6	240
valid_sources[0x69]	3241	1			T1	21		T3	5		T7	6
valid_sources[0x6a]	3917	1			T1	9		T3	6		T5	3
valid_sources[0x6b]	3428	1			T1	11		T5	8		T7	4
valid_sources[0x6c]	6369	1			T1	25		T5	11		T6	197
valid_sources[0x6d]	3811	1			T1	21		T3	1		T5	21
valid_sources[0x6e]	4092	1			T1	26		T5	9		T6	68
valid_sources[0x6f]	3904	1			T1	5		T5	1		T7	4
valid_sources[0x70]	3280	1			T1	20		T3	10		T4	1
valid_sources[0x71]	3662	1			T5	5		T6	259		T7	2
valid_sources[0x72]	3531	1			T1	8		T5	6		T6	67
valid_sources[0x73]	3133	1			T1	18		T5	29		T7	3
valid_sources[0x74]	3630	1			T1	11		T5	14		T6	387
valid_sources[0x75]	3562	1			T1	10		T4	1		T5	38
valid_sources[0x76]	3507	1			T1	26		T5	15		T7	2
valid_sources[0x77]	3258	1			T1	22		T5	27		T7	12
valid_sources[0x78]	5143	1			T1	14		T5	10		T7	3
valid_sources[0x79]	4142	1			T1	9		T5	2		T7	7
valid_sources[0x7a]	4213	1			T1	9		T5	35		T7	3
valid_sources[0x7b]	3417	1			T1	5		T3	2		T5	3
valid_sources[0x7c]	3371	1			T1	17		T5	10		T7	4
valid_sources[0x7d]	4735	1			T1	4		T5	9		T6	3
valid_sources[0x7e]	3837	1			T1	8		T5	14		T7	8
valid_sources[0x7f]	3489	1			T1	17		T5	6		T7	3
valid_sources[0x80]	4475	1			T1	11		T5	6		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

250769

1

T1

645

T3

42

T5

674

values[0x0]

all_enables

biggest_size

81207

1

T1

228

T3

16

T4

2

values[0x1]

all_enables

biggest_size

43736

1

T1

113

T3

10

T5

155