Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11535100	13461	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11535100	124296	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11535100	6787679	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11535100	198011	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11535100	13461	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11535100	124296	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11535100	6787679	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11535100	198011	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	13461	0	0
T1	29642	48	0	0
T2	5127	0	0	0
T3	2158	4	0	0
T4	1322	0	0	0
T5	26091	75	0	0
T6	100158	197	0	0
T7	11502	0	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	12	0	0
T12	0	4	0	0
T13	0	75	0	0
T14	0	75	0	0
T16	0	19	0	0
T27	0	16	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	124296	0	0
T1	29642	435	0	0
T2	5127	0	0	0
T3	2158	37	0	0
T4	1322	0	0	0
T5	26091	715	0	0
T6	100158	1797	0	0
T7	11502	0	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	108	0	0
T12	0	38	0	0
T13	0	709	0	0
T14	0	714	0	0
T16	0	171	0	0
T27	0	144	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	6787679	0	0
T1	29642	22849	0	0
T2	5127	589	0	0
T3	2158	1201	0	0
T4	1322	709	0	0
T5	26091	8778	0	0
T6	100158	50086	0	0
T7	11502	10928	0	0
T8	2113	1465	0	0
T9	1732	1107	0	0
T10	3387	2548	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	198011	0	0
T1	29642	696	0	0
T2	5127	0	0	0
T3	2158	64	0	0
T4	1322	0	0	0
T5	26091	1125	0	0
T6	100158	2902	0	0
T7	11502	0	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	188	0	0
T12	0	66	0	0
T13	0	1102	0	0
T14	0	1012	0	0
T16	0	264	0	0
T27	0	234	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	13461	0	0
T1	29642	48	0	0
T2	5127	0	0	0
T3	2158	4	0	0
T4	1322	0	0	0
T5	26091	75	0	0
T6	100158	197	0	0
T7	11502	0	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	12	0	0
T12	0	4	0	0
T13	0	75	0	0
T14	0	75	0	0
T16	0	19	0	0
T27	0	16	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	124296	0	0
T1	29642	435	0	0
T2	5127	0	0	0
T3	2158	37	0	0
T4	1322	0	0	0
T5	26091	715	0	0
T6	100158	1797	0	0
T7	11502	0	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	108	0	0
T12	0	38	0	0
T13	0	709	0	0
T14	0	714	0	0
T16	0	171	0	0
T27	0	144	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	6787679	0	0
T1	29642	22849	0	0
T2	5127	589	0	0
T3	2158	1201	0	0
T4	1322	709	0	0
T5	26091	8778	0	0
T6	100158	50086	0	0
T7	11502	10928	0	0
T8	2113	1465	0	0
T9	1732	1107	0	0
T10	3387	2548	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	198011	0	0
T1	29642	696	0	0
T2	5127	0	0	0
T3	2158	64	0	0
T4	1322	0	0	0
T5	26091	1125	0	0
T6	100158	2902	0	0
T7	11502	0	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	188	0	0
T12	0	66	0	0
T13	0	1102	0	0
T14	0	1012	0	0
T16	0	264	0	0
T27	0	234	0	0