Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54115228	8657	0	0
CascadeEffAonToRstPorAboveRise_A	54115228	8657	0	0
CascadeEffAonToRstPorIoAboveFall_A	51948604	8657	0	0
CascadeEffAonToRstPorIoAboveRise_A	51948604	8657	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25975418	8657	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25975418	8657	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12987383	8657	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12987383	8657	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25975356	8657	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25975356	8657	0	0
CascadeLcToLcAboveFall_A	54115228	22118	0	0
CascadeLcToLcAboveRise_A	54115228	22118	0	0
CascadeLcToLcAonAboveFall_A	1641270	22118	0	0
CascadeLcToLcAonAboveRise_A	1641270	22118	0	0
CascadeLcToLcShadowedAboveFall_A	54115228	22118	0	0
CascadeLcToLcShadowedAboveRise_A	54115228	22118	0	0
CascadePorToAonAboveFall_A	1641270	6964	0	0
CascadeSysToSysAboveFall_A	54115228	22118	0	0
CascadeSysToSysAboveRise_A	54115228	22118	0	0
ScanRstToAonRise_A	1641270	211	0	0
StablePorToAonRise_A	1641270	8657	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11535100	22118	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11535100	22118	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11535100	22118	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11535100	22118	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12987383	22118	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12987383	22118	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11535100	22118	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11535100	22118	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11535100	22118	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11535100	22118	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	8657	0	0
T1	143523	14	0	0
T2	24457	8	0	0
T3	10396	2	0	0
T4	5688	1	0	0
T5	121616	27	0	0
T6	523207	106	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	8657	0	0
T1	143523	14	0	0
T2	24457	8	0	0
T3	10396	2	0	0
T4	5688	1	0	0
T5	121616	27	0	0
T6	523207	106	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51948604	8657	0	0
T1	137781	14	0	0
T2	23453	8	0	0
T3	9981	2	0	0
T4	5461	1	0	0
T5	116711	27	0	0
T6	502290	106	0	0
T7	46373	1	0	0
T8	8532	1	0	0
T9	7102	1	0	0
T10	16466	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51948604	8657	0	0
T1	137781	14	0	0
T2	23453	8	0	0
T3	9981	2	0	0
T4	5461	1	0	0
T5	116711	27	0	0
T6	502290	106	0	0
T7	46373	1	0	0
T8	8532	1	0	0
T9	7102	1	0	0
T10	16466	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25975418	8657	0	0
T1	68896	14	0	0
T2	11724	8	0	0
T3	4989	2	0	0
T4	2729	1	0	0
T5	58377	27	0	0
T6	251122	106	0	0
T7	23188	1	0	0
T8	4265	1	0	0
T9	3550	1	0	0
T10	8233	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25975418	8657	0	0
T1	68896	14	0	0
T2	11724	8	0	0
T3	4989	2	0	0
T4	2729	1	0	0
T5	58377	27	0	0
T6	251122	106	0	0
T7	23188	1	0	0
T8	4265	1	0	0
T9	3550	1	0	0
T10	8233	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12987383	8657	0	0
T1	34444	14	0	0
T2	5865	8	0	0
T3	2496	2	0	0
T4	1364	1	0	0
T5	29180	27	0	0
T6	125563	106	0	0
T7	11593	1	0	0
T8	2132	1	0	0
T9	1774	1	0	0
T10	4116	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12987383	8657	0	0
T1	34444	14	0	0
T2	5865	8	0	0
T3	2496	2	0	0
T4	1364	1	0	0
T5	29180	27	0	0
T6	125563	106	0	0
T7	11593	1	0	0
T8	2132	1	0	0
T9	1774	1	0	0
T10	4116	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25975356	8657	0	0
T1	68897	14	0	0
T2	11730	8	0	0
T3	4990	2	0	0
T4	2730	1	0	0
T5	58372	27	0	0
T6	251130	106	0	0
T7	23188	1	0	0
T8	4265	1	0	0
T9	3550	1	0	0
T10	8234	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25975356	8657	0	0
T1	68897	14	0	0
T2	11730	8	0	0
T3	4990	2	0	0
T4	2730	1	0	0
T5	58372	27	0	0
T6	251130	106	0	0
T7	23188	1	0	0
T8	4265	1	0	0
T9	3550	1	0	0
T10	8234	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	22118	0	0
T1	143523	62	0	0
T2	24457	8	0	0
T3	10396	6	0	0
T4	5688	1	0	0
T5	121616	102	0	0
T6	523207	303	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	13	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	22118	0	0
T1	143523	62	0	0
T2	24457	8	0	0
T3	10396	6	0	0
T4	5688	1	0	0
T5	121616	102	0	0
T6	523207	303	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	13	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641270	22118	0	0
T1	4391	62	0	0
T2	735	8	0	0
T3	311	6	0	0
T4	170	1	0	0
T5	3663	102	0	0
T6	16025	303	0	0
T7	1448	1	0	0
T8	265	1	0	0
T9	220	1	0	0
T10	512	13	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641270	22118	0	0
T1	4391	62	0	0
T2	735	8	0	0
T3	311	6	0	0
T4	170	1	0	0
T5	3663	102	0	0
T6	16025	303	0	0
T7	1448	1	0	0
T8	265	1	0	0
T9	220	1	0	0
T10	512	13	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	22118	0	0
T1	143523	62	0	0
T2	24457	8	0	0
T3	10396	6	0	0
T4	5688	1	0	0
T5	121616	102	0	0
T6	523207	303	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	13	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	22118	0	0
T1	143523	62	0	0
T2	24457	8	0	0
T3	10396	6	0	0
T4	5688	1	0	0
T5	121616	102	0	0
T6	523207	303	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	13	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641270	6964	0	0
T1	4391	6	0	0
T2	735	8	0	0
T3	311	1	0	0
T4	170	1	0	0
T5	3663	27	0	0
T6	16025	61	0	0
T7	1448	1	0	0
T8	265	1	0	0
T9	220	1	0	0
T10	512	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	22118	0	0
T1	143523	62	0	0
T2	24457	8	0	0
T3	10396	6	0	0
T4	5688	1	0	0
T5	121616	102	0	0
T6	523207	303	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	13	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54115228	22118	0	0
T1	143523	62	0	0
T2	24457	8	0	0
T3	10396	6	0	0
T4	5688	1	0	0
T5	121616	102	0	0
T6	523207	303	0	0
T7	48307	1	0	0
T8	8888	1	0	0
T9	7397	1	0	0
T10	17153	13	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641270	211	0	0
T1	4391	1	0	0
T2	735	0	0	0
T3	311	1	0	0
T4	170	0	0	0
T5	3663	0	0	0
T6	16025	2	0	0
T7	1448	0	0	0
T8	265	0	0	0
T9	220	0	0	0
T10	512	0	0	0
T29	0	1	0	0
T33	0	1	0	0
T56	0	2	0	0
T89	0	4	0	0
T90	0	2	0	0
T91	0	10	0	0
T93	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641270	8657	0	0
T1	4391	14	0	0
T2	735	8	0	0
T3	311	2	0	0
T4	170	1	0	0
T5	3663	27	0	0
T6	16025	106	0	0
T7	1448	1	0	0
T8	265	1	0	0
T9	220	1	0	0
T10	512	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12987383	22118	0	0
T1	34444	62	0	0
T2	5865	8	0	0
T3	2496	6	0	0
T4	1364	1	0	0
T5	29180	102	0	0
T6	125563	303	0	0
T7	11593	1	0	0
T8	2132	1	0	0
T9	1774	1	0	0
T10	4116	13	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12987383	22118	0	0
T1	34444	62	0	0
T2	5865	8	0	0
T3	2496	6	0	0
T4	1364	1	0	0
T5	29180	102	0	0
T6	125563	303	0	0
T7	11593	1	0	0
T8	2132	1	0	0
T9	1774	1	0	0
T10	4116	13	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11535100	22118	0	0
T1	29642	62	0	0
T2	5127	8	0	0
T3	2158	6	0	0
T4	1322	1	0	0
T5	26091	102	0	0
T6	100158	303	0	0
T7	11502	1	0	0
T8	2113	1	0	0
T9	1732	1	0	0
T10	3387	13	0	0