Line Coverage for Module :
rstmgr_sw_rst_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
ALWAYS | 21 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
21 |
8 |
8 |
Cond Coverage for Module :
rstmgr_sw_rst_sva_if
| Total | Covered | Percent |
Conditions | 24 | 24 | 100.00 |
Logical | 24 | 24 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T10 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 21
EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T11 |
1 | 0 | Covered | T1,T2,T3 |
Assert Coverage for Module :
rstmgr_sw_rst_sva_if
Assertion Details
gen_assertions[0].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14329 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
216 |
0 |
0 |
T7 |
11593 |
6 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[0].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1065 |
0 |
0 |
T6 |
125563 |
20 |
0 |
0 |
T7 |
11593 |
6 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
3 |
0 |
0 |
T11 |
10955 |
5 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T16 |
0 |
9 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T63 |
0 |
2 |
0 |
0 |
T87 |
0 |
3 |
0 |
0 |
T88 |
0 |
1 |
0 |
0 |
gen_assertions[0].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14329 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
216 |
0 |
0 |
T7 |
11593 |
6 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[0].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1065 |
0 |
0 |
T6 |
125563 |
20 |
0 |
0 |
T7 |
11593 |
6 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
3 |
0 |
0 |
T11 |
10955 |
5 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T16 |
0 |
9 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T63 |
0 |
2 |
0 |
0 |
T87 |
0 |
3 |
0 |
0 |
T88 |
0 |
1 |
0 |
0 |
gen_assertions[1].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51948604 |
13038 |
0 |
0 |
T1 |
137781 |
43 |
0 |
0 |
T2 |
23453 |
0 |
0 |
0 |
T3 |
9981 |
4 |
0 |
0 |
T4 |
5461 |
0 |
0 |
0 |
T5 |
116711 |
67 |
0 |
0 |
T6 |
502290 |
194 |
0 |
0 |
T7 |
46373 |
9 |
0 |
0 |
T8 |
8532 |
0 |
0 |
0 |
T9 |
7102 |
0 |
0 |
0 |
T10 |
16466 |
12 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
67 |
0 |
0 |
T14 |
0 |
55 |
0 |
0 |
gen_assertions[1].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51948604 |
988 |
0 |
0 |
T6 |
502290 |
24 |
0 |
0 |
T7 |
46373 |
9 |
0 |
0 |
T8 |
8532 |
0 |
0 |
0 |
T9 |
7102 |
0 |
0 |
0 |
T10 |
16466 |
0 |
0 |
0 |
T11 |
43824 |
7 |
0 |
0 |
T12 |
13176 |
0 |
0 |
0 |
T13 |
180661 |
0 |
0 |
0 |
T14 |
226333 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
23397 |
0 |
0 |
0 |
T63 |
0 |
4 |
0 |
0 |
T87 |
0 |
5 |
0 |
0 |
T89 |
0 |
30 |
0 |
0 |
T90 |
0 |
31 |
0 |
0 |
T91 |
0 |
21 |
0 |
0 |
T92 |
0 |
5 |
0 |
0 |
gen_assertions[1].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51948604 |
13038 |
0 |
0 |
T1 |
137781 |
43 |
0 |
0 |
T2 |
23453 |
0 |
0 |
0 |
T3 |
9981 |
4 |
0 |
0 |
T4 |
5461 |
0 |
0 |
0 |
T5 |
116711 |
67 |
0 |
0 |
T6 |
502290 |
194 |
0 |
0 |
T7 |
46373 |
9 |
0 |
0 |
T8 |
8532 |
0 |
0 |
0 |
T9 |
7102 |
0 |
0 |
0 |
T10 |
16466 |
12 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
67 |
0 |
0 |
T14 |
0 |
55 |
0 |
0 |
gen_assertions[1].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51948604 |
988 |
0 |
0 |
T6 |
502290 |
24 |
0 |
0 |
T7 |
46373 |
9 |
0 |
0 |
T8 |
8532 |
0 |
0 |
0 |
T9 |
7102 |
0 |
0 |
0 |
T10 |
16466 |
0 |
0 |
0 |
T11 |
43824 |
7 |
0 |
0 |
T12 |
13176 |
0 |
0 |
0 |
T13 |
180661 |
0 |
0 |
0 |
T14 |
226333 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
23397 |
0 |
0 |
0 |
T63 |
0 |
4 |
0 |
0 |
T87 |
0 |
5 |
0 |
0 |
T89 |
0 |
30 |
0 |
0 |
T90 |
0 |
31 |
0 |
0 |
T91 |
0 |
21 |
0 |
0 |
T92 |
0 |
5 |
0 |
0 |
gen_assertions[2].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975418 |
13106 |
0 |
0 |
T1 |
68896 |
43 |
0 |
0 |
T2 |
11724 |
0 |
0 |
0 |
T3 |
4989 |
4 |
0 |
0 |
T4 |
2729 |
0 |
0 |
0 |
T5 |
58377 |
67 |
0 |
0 |
T6 |
251122 |
191 |
0 |
0 |
T7 |
23188 |
11 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8233 |
12 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
67 |
0 |
0 |
T14 |
0 |
55 |
0 |
0 |
gen_assertions[2].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975418 |
1008 |
0 |
0 |
T6 |
251122 |
20 |
0 |
0 |
T7 |
23188 |
11 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8233 |
0 |
0 |
0 |
T11 |
21912 |
6 |
0 |
0 |
T12 |
6587 |
0 |
0 |
0 |
T13 |
90333 |
0 |
0 |
0 |
T14 |
113190 |
0 |
0 |
0 |
T17 |
11699 |
0 |
0 |
0 |
T63 |
0 |
3 |
0 |
0 |
T87 |
0 |
5 |
0 |
0 |
T89 |
0 |
25 |
0 |
0 |
T90 |
0 |
28 |
0 |
0 |
T91 |
0 |
25 |
0 |
0 |
T92 |
0 |
10 |
0 |
0 |
T93 |
0 |
7 |
0 |
0 |
gen_assertions[2].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975418 |
13106 |
0 |
0 |
T1 |
68896 |
43 |
0 |
0 |
T2 |
11724 |
0 |
0 |
0 |
T3 |
4989 |
4 |
0 |
0 |
T4 |
2729 |
0 |
0 |
0 |
T5 |
58377 |
67 |
0 |
0 |
T6 |
251122 |
191 |
0 |
0 |
T7 |
23188 |
11 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8233 |
12 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
67 |
0 |
0 |
T14 |
0 |
55 |
0 |
0 |
gen_assertions[2].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975418 |
1008 |
0 |
0 |
T6 |
251122 |
20 |
0 |
0 |
T7 |
23188 |
11 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8233 |
0 |
0 |
0 |
T11 |
21912 |
6 |
0 |
0 |
T12 |
6587 |
0 |
0 |
0 |
T13 |
90333 |
0 |
0 |
0 |
T14 |
113190 |
0 |
0 |
0 |
T17 |
11699 |
0 |
0 |
0 |
T63 |
0 |
3 |
0 |
0 |
T87 |
0 |
5 |
0 |
0 |
T89 |
0 |
25 |
0 |
0 |
T90 |
0 |
28 |
0 |
0 |
T91 |
0 |
25 |
0 |
0 |
T92 |
0 |
10 |
0 |
0 |
T93 |
0 |
7 |
0 |
0 |
gen_assertions[3].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975356 |
13162 |
0 |
0 |
T1 |
68897 |
43 |
0 |
0 |
T2 |
11730 |
0 |
0 |
0 |
T3 |
4990 |
4 |
0 |
0 |
T4 |
2730 |
0 |
0 |
0 |
T5 |
58372 |
67 |
0 |
0 |
T6 |
251130 |
191 |
0 |
0 |
T7 |
23188 |
10 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8234 |
12 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
67 |
0 |
0 |
T14 |
0 |
55 |
0 |
0 |
gen_assertions[3].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975356 |
1059 |
0 |
0 |
T6 |
251130 |
19 |
0 |
0 |
T7 |
23188 |
10 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8234 |
0 |
0 |
0 |
T11 |
21912 |
9 |
0 |
0 |
T12 |
6587 |
0 |
0 |
0 |
T13 |
90323 |
0 |
0 |
0 |
T14 |
113181 |
0 |
0 |
0 |
T17 |
11697 |
0 |
0 |
0 |
T63 |
0 |
7 |
0 |
0 |
T87 |
0 |
6 |
0 |
0 |
T89 |
0 |
25 |
0 |
0 |
T90 |
0 |
31 |
0 |
0 |
T91 |
0 |
22 |
0 |
0 |
T92 |
0 |
11 |
0 |
0 |
T93 |
0 |
4 |
0 |
0 |
gen_assertions[3].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975356 |
13162 |
0 |
0 |
T1 |
68897 |
43 |
0 |
0 |
T2 |
11730 |
0 |
0 |
0 |
T3 |
4990 |
4 |
0 |
0 |
T4 |
2730 |
0 |
0 |
0 |
T5 |
58372 |
67 |
0 |
0 |
T6 |
251130 |
191 |
0 |
0 |
T7 |
23188 |
10 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8234 |
12 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
67 |
0 |
0 |
T14 |
0 |
55 |
0 |
0 |
gen_assertions[3].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
25975356 |
1059 |
0 |
0 |
T6 |
251130 |
19 |
0 |
0 |
T7 |
23188 |
10 |
0 |
0 |
T8 |
4265 |
0 |
0 |
0 |
T9 |
3550 |
0 |
0 |
0 |
T10 |
8234 |
0 |
0 |
0 |
T11 |
21912 |
9 |
0 |
0 |
T12 |
6587 |
0 |
0 |
0 |
T13 |
90323 |
0 |
0 |
0 |
T14 |
113181 |
0 |
0 |
0 |
T17 |
11697 |
0 |
0 |
0 |
T63 |
0 |
7 |
0 |
0 |
T87 |
0 |
6 |
0 |
0 |
T89 |
0 |
25 |
0 |
0 |
T90 |
0 |
31 |
0 |
0 |
T91 |
0 |
22 |
0 |
0 |
T92 |
0 |
11 |
0 |
0 |
T93 |
0 |
4 |
0 |
0 |
gen_assertions[4].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1641270 |
21940 |
0 |
0 |
T1 |
4391 |
62 |
0 |
0 |
T2 |
735 |
3 |
0 |
0 |
T3 |
311 |
5 |
0 |
0 |
T4 |
170 |
1 |
0 |
0 |
T5 |
3663 |
76 |
0 |
0 |
T6 |
16025 |
311 |
0 |
0 |
T7 |
1448 |
13 |
0 |
0 |
T8 |
265 |
1 |
0 |
0 |
T9 |
220 |
1 |
0 |
0 |
T10 |
512 |
13 |
0 |
0 |
gen_assertions[4].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1641270 |
1064 |
0 |
0 |
T6 |
16025 |
20 |
0 |
0 |
T7 |
1448 |
12 |
0 |
0 |
T8 |
265 |
0 |
0 |
0 |
T9 |
220 |
0 |
0 |
0 |
T10 |
512 |
0 |
0 |
0 |
T11 |
1369 |
10 |
0 |
0 |
T12 |
411 |
0 |
0 |
0 |
T13 |
5660 |
0 |
0 |
0 |
T14 |
7088 |
0 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T63 |
0 |
8 |
0 |
0 |
T87 |
0 |
7 |
0 |
0 |
T89 |
0 |
29 |
0 |
0 |
T90 |
0 |
32 |
0 |
0 |
T91 |
0 |
20 |
0 |
0 |
T92 |
0 |
9 |
0 |
0 |
gen_assertions[4].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1641270 |
21940 |
0 |
0 |
T1 |
4391 |
62 |
0 |
0 |
T2 |
735 |
3 |
0 |
0 |
T3 |
311 |
5 |
0 |
0 |
T4 |
170 |
1 |
0 |
0 |
T5 |
3663 |
76 |
0 |
0 |
T6 |
16025 |
311 |
0 |
0 |
T7 |
1448 |
13 |
0 |
0 |
T8 |
265 |
1 |
0 |
0 |
T9 |
220 |
1 |
0 |
0 |
T10 |
512 |
13 |
0 |
0 |
gen_assertions[4].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1641270 |
1064 |
0 |
0 |
T6 |
16025 |
20 |
0 |
0 |
T7 |
1448 |
12 |
0 |
0 |
T8 |
265 |
0 |
0 |
0 |
T9 |
220 |
0 |
0 |
0 |
T10 |
512 |
0 |
0 |
0 |
T11 |
1369 |
10 |
0 |
0 |
T12 |
411 |
0 |
0 |
0 |
T13 |
5660 |
0 |
0 |
0 |
T14 |
7088 |
0 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T63 |
0 |
8 |
0 |
0 |
T87 |
0 |
7 |
0 |
0 |
T89 |
0 |
29 |
0 |
0 |
T90 |
0 |
32 |
0 |
0 |
T91 |
0 |
20 |
0 |
0 |
T92 |
0 |
9 |
0 |
0 |
gen_assertions[5].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14556 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
214 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[5].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1126 |
0 |
0 |
T6 |
125563 |
18 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
0 |
0 |
0 |
T11 |
10955 |
9 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T63 |
0 |
9 |
0 |
0 |
T87 |
0 |
8 |
0 |
0 |
T89 |
0 |
29 |
0 |
0 |
T90 |
0 |
26 |
0 |
0 |
T91 |
0 |
26 |
0 |
0 |
T92 |
0 |
12 |
0 |
0 |
gen_assertions[5].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14556 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
214 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[5].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1126 |
0 |
0 |
T6 |
125563 |
18 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
0 |
0 |
0 |
T11 |
10955 |
9 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T63 |
0 |
9 |
0 |
0 |
T87 |
0 |
8 |
0 |
0 |
T89 |
0 |
29 |
0 |
0 |
T90 |
0 |
26 |
0 |
0 |
T91 |
0 |
26 |
0 |
0 |
T92 |
0 |
12 |
0 |
0 |
gen_assertions[6].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14621 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
216 |
0 |
0 |
T7 |
11593 |
13 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
12 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[6].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1196 |
0 |
0 |
T6 |
125563 |
20 |
0 |
0 |
T7 |
11593 |
13 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
0 |
0 |
0 |
T11 |
10955 |
12 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T63 |
0 |
9 |
0 |
0 |
T87 |
0 |
9 |
0 |
0 |
T89 |
0 |
27 |
0 |
0 |
T90 |
0 |
26 |
0 |
0 |
T91 |
0 |
26 |
0 |
0 |
T92 |
0 |
13 |
0 |
0 |
gen_assertions[6].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14621 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
216 |
0 |
0 |
T7 |
11593 |
13 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
12 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[6].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1196 |
0 |
0 |
T6 |
125563 |
20 |
0 |
0 |
T7 |
11593 |
13 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
0 |
0 |
0 |
T11 |
10955 |
12 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T63 |
0 |
9 |
0 |
0 |
T87 |
0 |
9 |
0 |
0 |
T89 |
0 |
27 |
0 |
0 |
T90 |
0 |
26 |
0 |
0 |
T91 |
0 |
26 |
0 |
0 |
T92 |
0 |
13 |
0 |
0 |
gen_assertions[7].RstEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14689 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
217 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
13 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[7].RstEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1266 |
0 |
0 |
T6 |
125563 |
22 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
0 |
0 |
0 |
T11 |
10955 |
13 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T63 |
0 |
10 |
0 |
0 |
T87 |
0 |
12 |
0 |
0 |
T89 |
0 |
28 |
0 |
0 |
T90 |
0 |
32 |
0 |
0 |
T91 |
0 |
25 |
0 |
0 |
T92 |
0 |
13 |
0 |
0 |
gen_assertions[7].RstNOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
14689 |
0 |
0 |
T1 |
34444 |
48 |
0 |
0 |
T2 |
5865 |
0 |
0 |
0 |
T3 |
2496 |
4 |
0 |
0 |
T4 |
1364 |
0 |
0 |
0 |
T5 |
29180 |
75 |
0 |
0 |
T6 |
125563 |
217 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
12 |
0 |
0 |
T11 |
0 |
13 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
75 |
0 |
0 |
T14 |
0 |
75 |
0 |
0 |
gen_assertions[7].RstNOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12987383 |
1266 |
0 |
0 |
T6 |
125563 |
22 |
0 |
0 |
T7 |
11593 |
15 |
0 |
0 |
T8 |
2132 |
0 |
0 |
0 |
T9 |
1774 |
0 |
0 |
0 |
T10 |
4116 |
0 |
0 |
0 |
T11 |
10955 |
13 |
0 |
0 |
T12 |
3295 |
0 |
0 |
0 |
T13 |
45163 |
0 |
0 |
0 |
T14 |
56592 |
0 |
0 |
0 |
T17 |
5850 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T63 |
0 |
10 |
0 |
0 |
T87 |
0 |
12 |
0 |
0 |
T89 |
0 |
28 |
0 |
0 |
T90 |
0 |
32 |
0 |
0 |
T91 |
0 |
25 |
0 |
0 |
T92 |
0 |
13 |
0 |
0 |