Unified Coverage Report :: Module :: rstmgr_ctrl

Module : rstmgr_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_src	100.00	100.00	100.00
tb.dut.u_sys_src	100.00	100.00	100.00

---

Module Instance : tb.dut.u_lc_src

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_pd_n[0].u_pd_rst	100.00	100.00				100.00
gen_rst_pd_n[0].u_rst_pd_mux	100.00	100.00	100.00				100.00
u_aon_rst	100.00	100.00				100.00
u_rst_aon_mux	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sys_src

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_pd_n[0].u_pd_rst	100.00	100.00				100.00
gen_rst_pd_n[0].u_rst_pd_mux	100.00	100.00	100.00				100.00
u_aon_rst	100.00	100.00				100.00
u_rst_aon_mux	100.00	100.00	100.00				100.00

Line Coverage for Module : rstmgr_ctrl

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	52	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
52	1	1

---

Cond Coverage for Module : rstmgr_ctrl

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       59
 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)])
             ----1----   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_src

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	52	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
52	1	1

---

Cond Coverage for Instance : tb.dut.u_lc_src

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       59
 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)])
             ----1----   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_src

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	52	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
52	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_src

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       59
 EXPRESSION (rst_aon_n & rst_parent_ni[(DomainPdStartIdx + 0)])
             ----1----   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3