Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12277472	7702	0	0
alert_regwen_rd_A	12277472	3362	0	0
cpu_regwen_rd_A	12277472	3557	0	0
sw_rst_ctrl_n_0_rd_A	12277472	8758	0	0
sw_rst_ctrl_n_1_rd_A	12277472	8712	0	0
sw_rst_ctrl_n_2_rd_A	12277472	8546	0	0
sw_rst_ctrl_n_3_rd_A	12277472	8780	0	0
sw_rst_ctrl_n_4_rd_A	12277472	8498	0	0
sw_rst_ctrl_n_5_rd_A	12277472	8718	0	0
sw_rst_ctrl_n_6_rd_A	12277472	8462	0	0
sw_rst_ctrl_n_7_rd_A	12277472	8651	0	0
sw_rst_regwen_0_rd_A	12277472	4185	0	0
sw_rst_regwen_1_rd_A	12277472	4255	0	0
sw_rst_regwen_2_rd_A	12277472	4187	0	0
sw_rst_regwen_3_rd_A	12277472	4293	0	0
sw_rst_regwen_4_rd_A	12277472	4215	0	0
sw_rst_regwen_5_rd_A	12277472	4172	0	0
sw_rst_regwen_6_rd_A	12277472	4236	0	0
sw_rst_regwen_7_rd_A	12277472	4140	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	7702	0	0
T67	4137	263	0	0
T68	3273	9	0	0
T69	4535	15	0	0
T70	4254	18	0	0
T71	18746	1	0	0
T72	3771	514	0	0
T94	4077	16	0	0
T95	3187	233	0	0
T96	2251	6	0	0
T119	11014	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	3362	0	0
T20	2037	0	0	0
T34	48881	0	0	0
T44	5834	0	0	0
T49	0	73	0	0
T53	53112	0	0	0
T103	35646	49	0	0
T106	0	76	0	0
T107	0	88	0	0
T108	0	173	0	0
T129	0	57	0	0
T130	0	67	0	0
T131	0	223	0	0
T132	0	44	0	0
T133	0	475	0	0
T134	2394	0	0	0
T135	3883	0	0	0
T136	1789	0	0	0
T137	4411	0	0	0
T138	5826	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	3557	0	0
T20	2037	0	0	0
T34	48881	0	0	0
T44	5834	0	0	0
T49	0	69	0	0
T53	53112	0	0	0
T103	35646	88	0	0
T106	0	52	0	0
T107	0	120	0	0
T108	0	192	0	0
T129	0	57	0	0
T130	0	60	0	0
T131	0	225	0	0
T132	0	39	0	0
T133	0	397	0	0
T134	2394	0	0	0
T135	3883	0	0	0
T136	1789	0	0	0
T137	4411	0	0	0
T138	5826	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8758	0	0
T7	11502	122	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	169	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	24	0	0
T45	0	93	0	0
T49	0	37	0	0
T103	0	65	0	0
T138	0	84	0	0
T139	0	10	0	0
T140	0	161	0	0
T141	0	167	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8712	0	0
T7	11502	138	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	185	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	17	0	0
T45	0	68	0	0
T49	0	46	0	0
T103	0	70	0	0
T138	0	71	0	0
T139	0	13	0	0
T140	0	204	0	0
T141	0	189	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8546	0	0
T7	11502	132	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	176	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	10	0	0
T45	0	70	0	0
T49	0	23	0	0
T103	0	61	0	0
T138	0	55	0	0
T139	0	13	0	0
T140	0	188	0	0
T141	0	173	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8780	0	0
T7	11502	149	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	144	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	3	0	0
T45	0	79	0	0
T49	0	55	0	0
T103	0	80	0	0
T138	0	69	0	0
T139	0	13	0	0
T140	0	167	0	0
T141	0	212	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8498	0	0
T7	11502	160	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	184	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	17	0	0
T45	0	105	0	0
T49	0	23	0	0
T103	0	71	0	0
T138	0	80	0	0
T139	0	12	0	0
T140	0	174	0	0
T141	0	212	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8718	0	0
T7	11502	158	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	189	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	18	0	0
T45	0	86	0	0
T49	0	49	0	0
T103	0	77	0	0
T138	0	70	0	0
T139	0	18	0	0
T140	0	149	0	0
T141	0	219	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8462	0	0
T7	11502	98	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	168	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	20	0	0
T45	0	42	0	0
T49	0	26	0	0
T103	0	55	0	0
T138	0	67	0	0
T139	0	10	0	0
T140	0	176	0	0
T141	0	182	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	8651	0	0
T7	11502	115	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	178	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	19	0	0
T45	0	94	0	0
T49	0	38	0	0
T103	0	65	0	0
T138	0	72	0	0
T139	0	16	0	0
T140	0	197	0	0
T141	0	194	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4185	0	0
T7	11502	24	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	27	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	3	0	0
T45	0	13	0	0
T49	0	41	0	0
T103	0	79	0	0
T139	0	4	0	0
T140	0	32	0	0
T141	0	38	0	0
T142	0	37	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4255	0	0
T7	11502	6	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	29	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	8	0	0
T45	0	11	0	0
T49	0	58	0	0
T103	0	75	0	0
T139	0	4	0	0
T140	0	38	0	0
T141	0	30	0	0
T142	0	33	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4187	0	0
T7	11502	19	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	32	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	4	0	0
T45	0	22	0	0
T49	0	52	0	0
T103	0	60	0	0
T139	0	5	0	0
T140	0	28	0	0
T141	0	37	0	0
T142	0	29	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4293	0	0
T7	11502	30	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	30	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	8	0	0
T45	0	28	0	0
T49	0	44	0	0
T103	0	54	0	0
T139	0	8	0	0
T140	0	33	0	0
T141	0	38	0	0
T142	0	19	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4215	0	0
T7	11502	25	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	26	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	7	0	0
T45	0	22	0	0
T49	0	45	0	0
T103	0	71	0	0
T139	0	5	0	0
T140	0	36	0	0
T141	0	30	0	0
T142	0	38	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4172	0	0
T7	11502	15	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	30	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	7	0	0
T45	0	18	0	0
T49	0	57	0	0
T103	0	62	0	0
T139	0	10	0	0
T140	0	20	0	0
T141	0	37	0	0
T142	0	25	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4236	0	0
T7	11502	24	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	41	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	9	0	0
T45	0	26	0	0
T49	0	54	0	0
T103	0	51	0	0
T139	0	10	0	0
T140	0	28	0	0
T141	0	28	0	0
T142	0	36	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12277472	4140	0	0
T7	11502	20	0	0
T8	2113	0	0	0
T9	1732	0	0	0
T10	3387	0	0	0
T11	10937	30	0	0
T12	3003	0	0	0
T13	41885	0	0	0
T14	53311	0	0	0
T15	4552	0	0	0
T17	5686	0	0	0
T44	0	9	0	0
T45	0	14	0	0
T49	0	41	0	0
T103	0	52	0	0
T139	0	2	0	0
T140	0	11	0	0
T141	0	31	0	0
T142	0	22	0	0