Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	631016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

380085

1

T1

113

T2

1

T4

1094

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	541397	1			T1	145		T4	1500		T7	186
values[0x0]	234449	1			T1	67		T2	2		T4	831
values[0x1]	235255	1			T1	80		T2	4		T4	869

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	529169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

481932

1

T1

138

T2

2

T4

1425

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3852	1			T4	18		T8	1		T9	6
valid_sources[0x01]	3201	1			T1	6		T4	16		T8	13
valid_sources[0x02]	3130	1			T1	7		T4	3		T8	6
valid_sources[0x03]	4078	1			T4	16		T8	31		T9	4
valid_sources[0x04]	3705	1			T1	14		T4	14		T8	1
valid_sources[0x05]	3709	1			T4	8		T8	32		T9	1
valid_sources[0x06]	3417	1			T4	15		T8	8		T9	3
valid_sources[0x07]	3422	1			T4	9		T8	15		T9	2
valid_sources[0x08]	3820	1			T1	4		T4	21		T6	1
valid_sources[0x09]	3472	1			T4	17		T8	6		T9	3
valid_sources[0x0a]	3425	1			T4	17		T8	19		T9	5
valid_sources[0x0b]	3559	1			T4	8		T8	9		T9	5
valid_sources[0x0c]	3520	1			T4	18		T8	10		T9	1
valid_sources[0x0d]	3469	1			T4	12		T8	78		T9	3
valid_sources[0x0e]	3669	1			T4	2		T8	10		T9	4
valid_sources[0x0f]	3536	1			T4	27		T8	30		T9	1
valid_sources[0x10]	3791	1			T4	13		T8	17		T9	2
valid_sources[0x11]	3885	1			T4	7		T8	35		T9	4
valid_sources[0x12]	3653	1			T1	2		T4	2		T8	39
valid_sources[0x13]	3414	1			T4	1		T8	26		T9	1
valid_sources[0x14]	3563	1			T8	29		T9	4		T12	5
valid_sources[0x15]	4230	1			T4	18		T8	14		T9	4
valid_sources[0x16]	7253	1			T1	18		T4	16		T9	3
valid_sources[0x17]	3903	1			T4	30		T8	23		T9	4
valid_sources[0x18]	3928	1			T4	16		T8	15		T9	5
valid_sources[0x19]	4641	1			T4	19		T8	11		T9	2
valid_sources[0x1a]	7608	1			T4	22		T9	3		T14	11
valid_sources[0x1b]	4103	1			T4	31		T8	26		T9	4
valid_sources[0x1c]	7583	1			T4	16		T8	10		T9	2
valid_sources[0x1d]	3210	1			T1	8		T4	10		T8	3
valid_sources[0x1e]	3504	1			T4	8		T8	9		T9	4
valid_sources[0x1f]	3633	1			T4	9		T8	17		T9	2
valid_sources[0x20]	3505	1			T4	6		T8	6		T9	7
valid_sources[0x21]	3387	1			T4	13		T8	12		T9	3
valid_sources[0x22]	3561	1			T1	2		T4	24		T8	18
valid_sources[0x23]	3116	1			T4	29		T8	45		T9	4
valid_sources[0x24]	3323	1			T4	8		T8	22		T9	4
valid_sources[0x25]	3783	1			T4	9		T8	17		T9	3
valid_sources[0x26]	4954	1			T4	11		T8	4		T12	1
valid_sources[0x27]	4585	1			T4	10		T8	13		T9	2
valid_sources[0x28]	5237	1			T4	2		T8	29		T9	3
valid_sources[0x29]	3633	1			T4	12		T8	14		T9	8
valid_sources[0x2a]	6576	1			T4	9		T8	34		T9	3
valid_sources[0x2b]	3688	1			T4	26		T8	5		T9	3
valid_sources[0x2c]	3295	1			T1	7		T4	1		T8	41
valid_sources[0x2d]	3479	1			T4	3		T8	7		T9	7
valid_sources[0x2e]	3757	1			T4	7		T8	46		T9	1
valid_sources[0x2f]	3309	1			T4	14		T8	30		T9	2
valid_sources[0x30]	3635	1			T4	6		T8	10		T9	4
valid_sources[0x31]	4276	1			T4	11		T8	68		T9	2
valid_sources[0x32]	3706	1			T4	21		T8	16		T9	1
valid_sources[0x33]	3969	1			T4	15		T8	24		T9	4
valid_sources[0x34]	3743	1			T4	14		T8	54		T9	4
valid_sources[0x35]	4870	1			T4	11		T8	14		T9	6
valid_sources[0x36]	4467	1			T4	9		T8	26		T9	4
valid_sources[0x37]	3938	1			T4	12		T8	26		T9	3
valid_sources[0x38]	3384	1			T1	1		T4	17		T8	1
valid_sources[0x39]	4344	1			T4	3		T9	4		T13	3
valid_sources[0x3a]	3162	1			T4	27		T8	66		T9	3
valid_sources[0x3b]	3259	1			T4	22		T9	5		T12	3
valid_sources[0x3c]	3344	1			T4	3		T8	61		T9	3
valid_sources[0x3d]	4085	1			T4	26		T8	12		T9	2
valid_sources[0x3e]	4775	1			T4	10		T8	13		T9	3
valid_sources[0x3f]	3721	1			T8	33		T9	4		T14	17
valid_sources[0x40]	3345	1			T4	3		T8	18		T9	2
valid_sources[0x41]	4604	1			T4	14		T8	15		T12	2
valid_sources[0x42]	3490	1			T4	10		T8	3		T9	1
valid_sources[0x43]	3435	1			T4	11		T8	15		T9	3
valid_sources[0x44]	3749	1			T4	7		T6	1		T8	48
valid_sources[0x45]	3533	1			T4	38		T8	28		T9	1
valid_sources[0x46]	3387	1			T4	8		T8	32		T9	4
valid_sources[0x47]	3937	1			T4	19		T8	50		T9	5
valid_sources[0x48]	3583	1			T4	5		T8	16		T9	4
valid_sources[0x49]	3757	1			T4	4		T6	1		T8	9
valid_sources[0x4a]	3455	1			T4	26		T8	4		T9	7
valid_sources[0x4b]	4565	1			T4	2		T8	19		T9	3
valid_sources[0x4c]	3374	1			T4	3		T8	94		T9	3
valid_sources[0x4d]	3262	1			T4	15		T8	16		T9	6
valid_sources[0x4e]	3399	1			T4	5		T8	37		T9	6
valid_sources[0x4f]	3446	1			T4	5		T8	15		T9	4
valid_sources[0x50]	3723	1			T4	20		T8	47		T9	2
valid_sources[0x51]	3596	1			T4	3		T8	5		T9	1
valid_sources[0x52]	5343	1			T4	21		T8	16		T9	3
valid_sources[0x53]	3162	1			T4	11		T8	38		T9	7
valid_sources[0x54]	5326	1			T4	15		T8	7		T9	5
valid_sources[0x55]	3848	1			T4	23		T8	24		T9	2
valid_sources[0x56]	3487	1			T4	16		T8	30		T9	3
valid_sources[0x57]	3449	1			T1	8		T4	25		T8	4
valid_sources[0x58]	3094	1			T4	3		T8	9		T9	4
valid_sources[0x59]	3916	1			T1	5		T4	32		T6	1
valid_sources[0x5a]	6539	1			T4	7		T8	1		T9	5
valid_sources[0x5b]	4545	1			T4	4		T8	24		T12	1
valid_sources[0x5c]	4003	1			T4	25		T8	33		T9	2
valid_sources[0x5d]	4772	1			T1	2		T4	15		T7	379
valid_sources[0x5e]	4286	1			T4	7		T8	9		T9	8
valid_sources[0x5f]	3489	1			T1	5		T4	5		T8	39
valid_sources[0x60]	4378	1			T4	5		T8	21		T9	1
valid_sources[0x61]	3612	1			T4	8		T8	9		T9	7
valid_sources[0x62]	4109	1			T4	15		T8	26		T9	4
valid_sources[0x63]	3749	1			T4	5		T8	30		T9	3
valid_sources[0x64]	3563	1			T4	3		T6	1		T8	7
valid_sources[0x65]	3494	1			T4	11		T8	33		T9	3
valid_sources[0x66]	3406	1			T1	2		T4	27		T8	3
valid_sources[0x67]	4097	1			T4	15		T8	45		T9	5
valid_sources[0x68]	3718	1			T1	2		T4	13		T6	1
valid_sources[0x69]	4253	1			T1	3		T4	14		T8	16
valid_sources[0x6a]	3874	1			T4	10		T8	31		T9	4
valid_sources[0x6b]	6941	1			T1	10		T4	9		T8	9
valid_sources[0x6c]	3202	1			T4	22		T6	2		T8	24
valid_sources[0x6d]	4456	1			T4	17		T8	26		T9	4
valid_sources[0x6e]	3639	1			T4	46		T8	26		T9	2
valid_sources[0x6f]	4105	1			T4	21		T8	10		T9	3
valid_sources[0x70]	4354	1			T1	4		T4	10		T8	58
valid_sources[0x71]	3883	1			T4	6		T8	15		T9	3
valid_sources[0x72]	3207	1			T4	1		T8	37		T12	2
valid_sources[0x73]	3360	1			T4	12		T8	16		T9	1
valid_sources[0x74]	3981	1			T4	22		T8	70		T9	3
valid_sources[0x75]	3397	1			T4	8		T8	4		T9	4
valid_sources[0x76]	3882	1			T4	9		T8	10		T12	1
valid_sources[0x77]	5439	1			T4	8		T8	6		T9	4
valid_sources[0x78]	5607	1			T1	9		T4	9		T8	2
valid_sources[0x79]	3776	1			T4	17		T6	1		T9	6
valid_sources[0x7a]	3212	1			T4	15		T8	30		T9	1
valid_sources[0x7b]	4550	1			T1	1		T4	14		T8	15
valid_sources[0x7c]	3851	1			T4	3		T8	36		T9	7
valid_sources[0x7d]	3320	1			T4	9		T8	33		T9	1
valid_sources[0x7e]	3753	1			T4	18		T8	25		T9	10
valid_sources[0x7f]	3134	1			T1	5		T4	12		T8	23
valid_sources[0x80]	4628	1			T4	25		T8	27		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

254041

1

T1

72

T4

667

T7

82

values[0x0]

all_enables

biggest_size

82070

1

T1

23

T4

282

T6

3

values[0x1]

all_enables

biggest_size

43974

1

T1

18

T2

1

T4

145