Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T12
0	1	Covered	T8,T12,T14
1	0	Covered	T8,T14,T27

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T7,T8,T12
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55548206	9388	0	0
CascadeEffAonToRstPorAboveRise_A	55548206	9388	0	0
CascadeEffAonToRstPorIoAboveFall_A	53325023	9388	0	0
CascadeEffAonToRstPorIoAboveRise_A	53325023	9388	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26663245	9388	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26663245	9388	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13331368	9388	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13331368	9388	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26663046	9388	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26663046	9388	0	0
CascadeLcToLcAboveFall_A	55548206	22683	0	0
CascadeLcToLcAboveRise_A	55548206	22683	0	0
CascadeLcToLcAonAboveFall_A	1683364	22683	0	0
CascadeLcToLcAonAboveRise_A	1683364	22683	0	0
CascadeLcToLcShadowedAboveFall_A	55548206	22683	0	0
CascadeLcToLcShadowedAboveRise_A	55548206	22683	0	0
CascadePorToAonAboveFall_A	1683364	7563	0	0
CascadeSysToSysAboveFall_A	55548206	22683	0	0
CascadeSysToSysAboveRise_A	55548206	22683	0	0
ScanRstToAonRise_A	1683364	216	0	0
StablePorToAonRise_A	1683364	9388	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11766509	22683	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11766509	22683	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11766509	22683	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11766509	22683	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13331368	22683	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13331368	22683	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11766509	22683	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11766509	22683	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11766509	22683	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11766509	22683	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	9388	0	0
T1	24117	1	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	27	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	2	0	0
T8	358011	25	0	0
T9	45027	1	0	0
T10	7310	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	9388	0	0
T1	24117	1	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	27	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	2	0	0
T8	358011	25	0	0
T9	45027	1	0	0
T10	7310	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53325023	9388	0	0
T1	23151	1	0	0
T2	6231	1	0	0
T3	23300	8	0	0
T4	116280	27	0	0
T5	23350	8	0	0
T6	7208	1	0	0
T7	11563	2	0	0
T8	343666	25	0	0
T9	43225	1	0	0
T10	7017	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53325023	9388	0	0
T1	23151	1	0	0
T2	6231	1	0	0
T3	23300	8	0	0
T4	116280	27	0	0
T5	23350	8	0	0
T6	7208	1	0	0
T7	11563	2	0	0
T8	343666	25	0	0
T9	43225	1	0	0
T10	7017	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663245	9388	0	0
T1	11576	1	0	0
T2	3114	1	0	0
T3	11656	8	0	0
T4	58154	27	0	0
T5	11676	8	0	0
T6	3603	1	0	0
T7	5779	2	0	0
T8	171833	25	0	0
T9	21612	1	0	0
T10	3508	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663245	9388	0	0
T1	11576	1	0	0
T2	3114	1	0	0
T3	11656	8	0	0
T4	58154	27	0	0
T5	11676	8	0	0
T6	3603	1	0	0
T7	5779	2	0	0
T8	171833	25	0	0
T9	21612	1	0	0
T10	3508	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	9388	0	0
T1	5787	1	0	0
T2	1556	1	0	0
T3	5830	8	0	0
T4	29066	27	0	0
T5	5837	8	0	0
T6	1801	1	0	0
T7	2891	2	0	0
T8	85917	25	0	0
T9	10805	1	0	0
T10	1752	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	9388	0	0
T1	5787	1	0	0
T2	1556	1	0	0
T3	5830	8	0	0
T4	29066	27	0	0
T5	5837	8	0	0
T6	1801	1	0	0
T7	2891	2	0	0
T8	85917	25	0	0
T9	10805	1	0	0
T10	1752	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663046	9388	0	0
T1	11576	1	0	0
T2	3115	1	0	0
T3	11649	8	0	0
T4	58154	27	0	0
T5	11677	8	0	0
T6	3603	1	0	0
T7	5784	2	0	0
T8	171834	25	0	0
T9	21612	1	0	0
T10	3508	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663046	9388	0	0
T1	11576	1	0	0
T2	3115	1	0	0
T3	11649	8	0	0
T4	58154	27	0	0
T5	11677	8	0	0
T6	3603	1	0	0
T7	5784	2	0	0
T8	171834	25	0	0
T9	21612	1	0	0
T10	3508	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	22683	0	0
T1	24117	17	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	102	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	6	0	0
T8	358011	81	0	0
T9	45027	1	0	0
T10	7310	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	22683	0	0
T1	24117	17	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	102	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	6	0	0
T8	358011	81	0	0
T9	45027	1	0	0
T10	7310	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	22683	0	0
T1	722	17	0	0
T2	192	1	0	0
T3	730	8	0	0
T4	3649	102	0	0
T5	731	8	0	0
T6	224	1	0	0
T7	360	6	0	0
T8	10812	81	0	0
T9	1349	1	0	0
T10	217	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	22683	0	0
T1	722	17	0	0
T2	192	1	0	0
T3	730	8	0	0
T4	3649	102	0	0
T5	731	8	0	0
T6	224	1	0	0
T7	360	6	0	0
T8	10812	81	0	0
T9	1349	1	0	0
T10	217	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	22683	0	0
T1	24117	17	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	102	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	6	0	0
T8	358011	81	0	0
T9	45027	1	0	0
T10	7310	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	22683	0	0
T1	24117	17	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	102	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	6	0	0
T8	358011	81	0	0
T9	45027	1	0	0
T10	7310	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	7563	0	0
T1	722	1	0	0
T2	192	1	0	0
T3	730	8	0	0
T4	3649	27	0	0
T5	731	8	0	0
T6	224	1	0	0
T7	360	1	0	0
T8	10812	15	0	0
T9	1349	1	0	0
T10	217	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	22683	0	0
T1	24117	17	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	102	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	6	0	0
T8	358011	81	0	0
T9	45027	1	0	0
T10	7310	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55548206	22683	0	0
T1	24117	17	0	0
T2	6491	1	0	0
T3	24273	8	0	0
T4	121139	102	0	0
T5	24319	8	0	0
T6	7509	1	0	0
T7	12040	6	0	0
T8	358011	81	0	0
T9	45027	1	0	0
T10	7310	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	216	0	0
T12	337	1	0	0
T13	577	0	0	0
T14	4591	1	0	0
T15	294	0	0	0
T25	562	0	0	0
T26	344	0	0	0
T27	4427	0	0	0
T28	3670	0	0	0
T29	572	1	0	0
T30	731	0	0	0
T43	0	1	0	0
T52	0	3	0	0
T57	0	1	0	0
T88	0	1	0	0
T101	0	2	0	0
T102	0	2	0	0
T105	0	4	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	9388	0	0
T1	722	1	0	0
T2	192	1	0	0
T3	730	8	0	0
T4	3649	27	0	0
T5	731	8	0	0
T6	224	1	0	0
T7	360	2	0	0
T8	10812	25	0	0
T9	1349	1	0	0
T10	217	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	22683	0	0
T1	5787	17	0	0
T2	1556	1	0	0
T3	5830	8	0	0
T4	29066	102	0	0
T5	5837	8	0	0
T6	1801	1	0	0
T7	2891	6	0	0
T8	85917	81	0	0
T9	10805	1	0	0
T10	1752	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	22683	0	0
T1	5787	17	0	0
T2	1556	1	0	0
T3	5830	8	0	0
T4	29066	102	0	0
T5	5837	8	0	0
T6	1801	1	0	0
T7	2891	6	0	0
T8	85917	81	0	0
T9	10805	1	0	0
T10	1752	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11766509	22683	0	0
T1	4652	17	0	0
T2	1466	1	0	0
T3	5473	8	0	0
T4	26254	102	0	0
T5	5100	8	0	0
T6	1783	1	0	0
T7	2647	6	0	0
T8	79609	81	0	0
T9	10739	1	0	0
T10	1608	2	0	0