Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13331368	14059	0	0
gen_assertions[0].RstEnOn_A	13331368	923	0	0
gen_assertions[0].RstNOff_A	13331368	14059	0	0
gen_assertions[0].RstNOn_A	13331368	923	0	0
gen_assertions[1].RstEnOff_A	53325023	12792	0	0
gen_assertions[1].RstEnOn_A	53325023	895	0	0
gen_assertions[1].RstNOff_A	53325023	12792	0	0
gen_assertions[1].RstNOn_A	53325023	895	0	0
gen_assertions[2].RstEnOff_A	26663245	12881	0	0
gen_assertions[2].RstEnOn_A	26663245	944	0	0
gen_assertions[2].RstNOff_A	26663245	12881	0	0
gen_assertions[2].RstNOn_A	26663245	944	0	0
gen_assertions[3].RstEnOff_A	26663046	12893	0	0
gen_assertions[3].RstEnOn_A	26663046	949	0	0
gen_assertions[3].RstNOff_A	26663046	12893	0	0
gen_assertions[3].RstNOn_A	26663046	949	0	0
gen_assertions[4].RstEnOff_A	1683364	22346	0	0
gen_assertions[4].RstEnOn_A	1683364	998	0	0
gen_assertions[4].RstNOff_A	1683364	22346	0	0
gen_assertions[4].RstNOn_A	1683364	998	0	0
gen_assertions[5].RstEnOff_A	13331368	14313	0	0
gen_assertions[5].RstEnOn_A	13331368	1052	0	0
gen_assertions[5].RstNOff_A	13331368	14313	0	0
gen_assertions[5].RstNOn_A	13331368	1052	0	0
gen_assertions[6].RstEnOff_A	13331368	14378	0	0
gen_assertions[6].RstEnOn_A	13331368	1114	0	0
gen_assertions[6].RstNOff_A	13331368	14378	0	0
gen_assertions[6].RstNOn_A	13331368	1114	0	0
gen_assertions[7].RstEnOff_A	13331368	14407	0	0
gen_assertions[7].RstEnOn_A	13331368	1151	0	0
gen_assertions[7].RstNOff_A	13331368	14407	0	0
gen_assertions[7].RstNOn_A	13331368	1151	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14059	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	83	0	0
T9	10805	5	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	5	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	923	0	0
T1	5787	1	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	0	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	0	0	0
T8	85917	28	0	0
T9	10805	5	0	0
T10	1752	0	0	0
T12	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T52	0	16	0	0
T58	0	4	0	0
T62	0	2	0	0
T65	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14059	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	83	0	0
T9	10805	5	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	5	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	923	0	0
T1	5787	1	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	0	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	0	0	0
T8	85917	28	0	0
T9	10805	5	0	0
T10	1752	0	0	0
T12	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T52	0	16	0	0
T58	0	4	0	0
T62	0	2	0	0
T65	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53325023	12792	0	0
T1	23151	16	0	0
T2	6231	0	0	0
T3	23300	0	0	0
T4	116280	64	0	0
T5	23350	0	0	0
T6	7208	0	0	0
T7	11563	3	0	0
T8	343666	80	0	0
T9	43225	4	0	0
T10	7017	1	0	0
T11	0	1	0	0
T12	0	3	0	0
T13	0	11	0	0
T14	0	39	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53325023	895	0	0
T8	343666	32	0	0
T9	43225	4	0	0
T10	7017	0	0	0
T11	6646	0	0	0
T12	10855	0	0	0
T13	18503	0	0	0
T14	144681	0	0	0
T15	9425	0	0	0
T25	18062	0	0	0
T26	11058	2	0	0
T29	0	1	0	0
T44	0	1	0	0
T52	0	16	0	0
T58	0	4	0	0
T65	0	7	0	0
T87	0	5	0	0
T88	0	21	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53325023	12792	0	0
T1	23151	16	0	0
T2	6231	0	0	0
T3	23300	0	0	0
T4	116280	64	0	0
T5	23350	0	0	0
T6	7208	0	0	0
T7	11563	3	0	0
T8	343666	80	0	0
T9	43225	4	0	0
T10	7017	1	0	0
T11	0	1	0	0
T12	0	3	0	0
T13	0	11	0	0
T14	0	39	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53325023	895	0	0
T8	343666	32	0	0
T9	43225	4	0	0
T10	7017	0	0	0
T11	6646	0	0	0
T12	10855	0	0	0
T13	18503	0	0	0
T14	144681	0	0	0
T15	9425	0	0	0
T25	18062	0	0	0
T26	11058	2	0	0
T29	0	1	0	0
T44	0	1	0	0
T52	0	16	0	0
T58	0	4	0	0
T65	0	7	0	0
T87	0	5	0	0
T88	0	21	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663245	12881	0	0
T1	11576	16	0	0
T2	3114	0	0	0
T3	11656	0	0	0
T4	58154	64	0	0
T5	11676	0	0	0
T6	3603	0	0	0
T7	5779	3	0	0
T8	171833	79	0	0
T9	21612	5	0	0
T10	3508	1	0	0
T11	0	1	0	0
T12	0	3	0	0
T13	0	11	0	0
T14	0	39	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663245	944	0	0
T8	171833	30	0	0
T9	21612	5	0	0
T10	3508	0	0	0
T11	3322	0	0	0
T12	5429	0	0	0
T13	9251	0	0	0
T14	72347	0	0	0
T15	4711	0	0	0
T25	9031	0	0	0
T26	5529	4	0	0
T52	0	22	0	0
T58	0	5	0	0
T65	0	7	0	0
T87	0	7	0	0
T88	0	24	0	0
T89	0	1	0	0
T90	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663245	12881	0	0
T1	11576	16	0	0
T2	3114	0	0	0
T3	11656	0	0	0
T4	58154	64	0	0
T5	11676	0	0	0
T6	3603	0	0	0
T7	5779	3	0	0
T8	171833	79	0	0
T9	21612	5	0	0
T10	3508	1	0	0
T11	0	1	0	0
T12	0	3	0	0
T13	0	11	0	0
T14	0	39	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663245	944	0	0
T8	171833	30	0	0
T9	21612	5	0	0
T10	3508	0	0	0
T11	3322	0	0	0
T12	5429	0	0	0
T13	9251	0	0	0
T14	72347	0	0	0
T15	4711	0	0	0
T25	9031	0	0	0
T26	5529	4	0	0
T52	0	22	0	0
T58	0	5	0	0
T65	0	7	0	0
T87	0	7	0	0
T88	0	24	0	0
T89	0	1	0	0
T90	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663046	12893	0	0
T1	11576	16	0	0
T2	3115	0	0	0
T3	11649	0	0	0
T4	58154	64	0	0
T5	11677	0	0	0
T6	3603	0	0	0
T7	5784	4	0	0
T8	171834	83	0	0
T9	21612	5	0	0
T10	3508	1	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	11	0	0
T14	0	39	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663046	949	0	0
T7	5784	1	0	0
T8	171834	34	0	0
T9	21612	5	0	0
T10	3508	0	0	0
T11	3323	0	0	0
T12	5424	1	0	0
T13	9251	0	0	0
T14	72348	0	0	0
T15	4711	0	0	0
T25	9031	0	0	0
T26	0	4	0	0
T52	0	18	0	0
T58	0	5	0	0
T65	0	8	0	0
T87	0	8	0	0
T91	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663046	12893	0	0
T1	11576	16	0	0
T2	3115	0	0	0
T3	11649	0	0	0
T4	58154	64	0	0
T5	11677	0	0	0
T6	3603	0	0	0
T7	5784	4	0	0
T8	171834	83	0	0
T9	21612	5	0	0
T10	3508	1	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	11	0	0
T14	0	39	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26663046	949	0	0
T7	5784	1	0	0
T8	171834	34	0	0
T9	21612	5	0	0
T10	3508	0	0	0
T11	3323	0	0	0
T12	5424	1	0	0
T13	9251	0	0	0
T14	72348	0	0	0
T15	4711	0	0	0
T25	9031	0	0	0
T26	0	4	0	0
T52	0	18	0	0
T58	0	5	0	0
T65	0	8	0	0
T87	0	8	0	0
T91	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	22346	0	0
T1	722	17	0	0
T2	192	1	0	0
T3	730	3	0	0
T4	3649	75	0	0
T5	731	2	0	0
T6	224	1	0	0
T7	360	5	0	0
T8	10812	113	0	0
T9	1349	9	0	0
T10	217	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	998	0	0
T8	10812	33	0	0
T9	1349	8	0	0
T10	217	0	0	0
T11	206	0	0	0
T12	337	0	0	0
T13	577	0	0	0
T14	4591	0	0	0
T15	294	0	0	0
T25	562	0	0	0
T26	344	5	0	0
T52	0	15	0	0
T58	0	6	0	0
T65	0	9	0	0
T87	0	7	0	0
T88	0	26	0	0
T89	0	1	0	0
T92	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	22346	0	0
T1	722	17	0	0
T2	192	1	0	0
T3	730	3	0	0
T4	3649	75	0	0
T5	731	2	0	0
T6	224	1	0	0
T7	360	5	0	0
T8	10812	113	0	0
T9	1349	9	0	0
T10	217	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683364	998	0	0
T8	10812	33	0	0
T9	1349	8	0	0
T10	217	0	0	0
T11	206	0	0	0
T12	337	0	0	0
T13	577	0	0	0
T14	4591	0	0	0
T15	294	0	0	0
T25	562	0	0	0
T26	344	5	0	0
T52	0	15	0	0
T58	0	6	0	0
T65	0	9	0	0
T87	0	7	0	0
T88	0	26	0	0
T89	0	1	0	0
T92	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14313	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	88	0	0
T9	10805	9	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	5	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	1052	0	0
T8	85917	33	0	0
T9	10805	9	0	0
T10	1752	0	0	0
T11	1661	0	0	0
T12	2714	1	0	0
T13	4626	0	0	0
T14	36169	0	0	0
T15	2356	0	0	0
T25	4515	0	0	0
T26	2763	6	0	0
T52	0	14	0	0
T58	0	3	0	0
T65	0	8	0	0
T87	0	9	0	0
T88	0	23	0	0
T90	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14313	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	88	0	0
T9	10805	9	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	5	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	1052	0	0
T8	85917	33	0	0
T9	10805	9	0	0
T10	1752	0	0	0
T11	1661	0	0	0
T12	2714	1	0	0
T13	4626	0	0	0
T14	36169	0	0	0
T15	2356	0	0	0
T25	4515	0	0	0
T26	2763	6	0	0
T52	0	14	0	0
T58	0	3	0	0
T65	0	8	0	0
T87	0	9	0	0
T88	0	23	0	0
T90	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14378	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	89	0	0
T9	10805	10	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	1114	0	0
T8	85917	34	0	0
T9	10805	10	0	0
T10	1752	0	0	0
T11	1661	0	0	0
T12	2714	0	0	0
T13	4626	0	0	0
T14	36169	0	0	0
T15	2356	0	0	0
T25	4515	0	0	0
T26	2763	8	0	0
T44	0	1	0	0
T52	0	14	0	0
T58	0	4	0	0
T65	0	11	0	0
T87	0	11	0	0
T88	0	25	0	0
T93	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14378	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	89	0	0
T9	10805	10	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	1114	0	0
T8	85917	34	0	0
T9	10805	10	0	0
T10	1752	0	0	0
T11	1661	0	0	0
T12	2714	0	0	0
T13	4626	0	0	0
T14	36169	0	0	0
T15	2356	0	0	0
T25	4515	0	0	0
T26	2763	8	0	0
T44	0	1	0	0
T52	0	14	0	0
T58	0	4	0	0
T65	0	11	0	0
T87	0	11	0	0
T88	0	25	0	0
T93	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14407	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	86	0	0
T9	10805	11	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	1151	0	0
T8	85917	31	0	0
T9	10805	11	0	0
T10	1752	0	0	0
T11	1661	0	0	0
T12	2714	0	0	0
T13	4626	0	0	0
T14	36169	0	0	0
T15	2356	0	0	0
T25	4515	0	0	0
T26	2763	9	0	0
T44	0	1	0	0
T52	0	16	0	0
T58	0	5	0	0
T65	0	11	0	0
T87	0	13	0	0
T93	0	1	0	0
T94	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	14407	0	0
T1	5787	16	0	0
T2	1556	0	0	0
T3	5830	0	0	0
T4	29066	75	0	0
T5	5837	0	0	0
T6	1801	0	0	0
T7	2891	4	0	0
T8	85917	86	0	0
T9	10805	11	0	0
T10	1752	1	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	12	0	0
T14	0	39	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13331368	1151	0	0
T8	85917	31	0	0
T9	10805	11	0	0
T10	1752	0	0	0
T11	1661	0	0	0
T12	2714	0	0	0
T13	4626	0	0	0
T14	36169	0	0	0
T15	2356	0	0	0
T25	4515	0	0	0
T26	2763	9	0	0
T44	0	1	0	0
T52	0	16	0	0
T58	0	5	0	0
T65	0	11	0	0
T87	0	13	0	0
T93	0	1	0	0
T94	0	1	0	0