Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12498756	10122	0	0
alert_regwen_rd_A	12498756	4994	0	0
cpu_regwen_rd_A	12498756	5007	0	0
sw_rst_ctrl_n_0_rd_A	12498756	10686	0	0
sw_rst_ctrl_n_1_rd_A	12498756	10662	0	0
sw_rst_ctrl_n_2_rd_A	12498756	10525	0	0
sw_rst_ctrl_n_3_rd_A	12498756	10698	0	0
sw_rst_ctrl_n_4_rd_A	12498756	10537	0	0
sw_rst_ctrl_n_5_rd_A	12498756	10956	0	0
sw_rst_ctrl_n_6_rd_A	12498756	10581	0	0
sw_rst_ctrl_n_7_rd_A	12498756	10372	0	0
sw_rst_regwen_0_rd_A	12498756	5395	0	0
sw_rst_regwen_1_rd_A	12498756	5578	0	0
sw_rst_regwen_2_rd_A	12498756	5397	0	0
sw_rst_regwen_3_rd_A	12498756	5546	0	0
sw_rst_regwen_4_rd_A	12498756	5801	0	0
sw_rst_regwen_5_rd_A	12498756	5510	0	0
sw_rst_regwen_6_rd_A	12498756	5517	0	0
sw_rst_regwen_7_rd_A	12498756	5481	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10122	0	0
T67	2219	7	0	0
T68	3558	60	0	0
T69	9917	4	0	0
T70	8376	318	0	0
T71	6700	341	0	0
T72	12065	654	0	0
T95	3420	262	0	0
T96	11512	283	0	0
T97	20240	2	0	0
T99	10782	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	4994	0	0
T8	79609	29	0	0
T9	10739	0	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	59	0	0
T88	0	269	0	0
T101	0	96	0	0
T102	0	333	0	0
T105	0	308	0	0
T106	0	47	0	0
T129	0	152	0	0
T130	0	17	0	0
T131	0	63	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5007	0	0
T8	79609	60	0	0
T9	10739	0	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	61	0	0
T88	0	277	0	0
T101	0	74	0	0
T102	0	347	0	0
T105	0	318	0	0
T106	0	26	0	0
T129	0	125	0	0
T130	0	37	0	0
T131	0	58	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10686	0	0
T1	4652	34	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	452	0	0
T9	10739	138	0	0
T10	1608	0	0	0
T13	0	27	0	0
T51	0	38	0	0
T65	0	184	0	0
T88	0	632	0	0
T89	0	18	0	0
T92	0	15	0	0
T132	0	66	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10662	0	0
T1	4652	38	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	500	0	0
T9	10739	185	0	0
T10	1608	0	0	0
T13	0	39	0	0
T51	0	62	0	0
T65	0	170	0	0
T88	0	553	0	0
T89	0	17	0	0
T92	0	13	0	0
T132	0	54	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10525	0	0
T1	4652	39	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	483	0	0
T9	10739	170	0	0
T10	1608	0	0	0
T13	0	22	0	0
T51	0	44	0	0
T65	0	160	0	0
T88	0	566	0	0
T89	0	10	0	0
T92	0	19	0	0
T132	0	49	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10698	0	0
T1	4652	33	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	439	0	0
T9	10739	136	0	0
T10	1608	0	0	0
T13	0	26	0	0
T51	0	60	0	0
T65	0	193	0	0
T88	0	665	0	0
T89	0	19	0	0
T92	0	14	0	0
T132	0	48	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10537	0	0
T1	4652	35	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	462	0	0
T9	10739	170	0	0
T10	1608	0	0	0
T13	0	22	0	0
T51	0	62	0	0
T65	0	195	0	0
T88	0	592	0	0
T89	0	16	0	0
T92	0	5	0	0
T132	0	46	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10956	0	0
T1	4652	29	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	479	0	0
T9	10739	163	0	0
T10	1608	0	0	0
T13	0	35	0	0
T51	0	56	0	0
T65	0	142	0	0
T88	0	617	0	0
T89	0	17	0	0
T92	0	19	0	0
T132	0	59	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10581	0	0
T1	4652	45	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	448	0	0
T9	10739	145	0	0
T10	1608	0	0	0
T13	0	25	0	0
T51	0	57	0	0
T65	0	201	0	0
T88	0	641	0	0
T89	0	5	0	0
T92	0	18	0	0
T132	0	29	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	10372	0	0
T1	4652	52	0	0
T2	1466	0	0	0
T3	5473	0	0	0
T4	26254	0	0	0
T5	5100	0	0	0
T6	1783	0	0	0
T7	2647	0	0	0
T8	79609	462	0	0
T9	10739	154	0	0
T10	1608	0	0	0
T13	0	29	0	0
T51	0	36	0	0
T65	0	150	0	0
T88	0	570	0	0
T89	0	17	0	0
T92	0	17	0	0
T132	0	47	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5395	0	0
T8	79609	45	0	0
T9	10739	39	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	49	0	0
T65	0	35	0	0
T88	0	265	0	0
T89	0	3	0	0
T92	0	9	0	0
T101	0	87	0	0
T133	0	1	0	0
T134	0	38	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5578	0	0
T8	79609	64	0	0
T9	10739	38	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	48	0	0
T65	0	32	0	0
T88	0	257	0	0
T89	0	12	0	0
T92	0	2	0	0
T101	0	80	0	0
T102	0	337	0	0
T134	0	22	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5397	0	0
T8	79609	68	0	0
T9	10739	22	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	42	0	0
T65	0	40	0	0
T88	0	256	0	0
T89	0	2	0	0
T92	0	8	0	0
T101	0	68	0	0
T133	0	1	0	0
T134	0	33	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5546	0	0
T8	79609	60	0	0
T9	10739	29	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	49	0	0
T65	0	41	0	0
T88	0	240	0	0
T89	0	8	0	0
T92	0	8	0	0
T101	0	93	0	0
T133	0	5	0	0
T134	0	53	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5801	0	0
T8	79609	58	0	0
T9	10739	36	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	55	0	0
T65	0	38	0	0
T88	0	278	0	0
T89	0	4	0	0
T92	0	8	0	0
T101	0	63	0	0
T133	0	5	0	0
T134	0	25	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5510	0	0
T8	79609	61	0	0
T9	10739	29	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	53	0	0
T65	0	27	0	0
T88	0	317	0	0
T89	0	12	0	0
T92	0	12	0	0
T101	0	76	0	0
T133	0	7	0	0
T134	0	23	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5517	0	0
T8	79609	75	0	0
T9	10739	19	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	59	0	0
T65	0	24	0	0
T88	0	273	0	0
T89	0	5	0	0
T101	0	70	0	0
T102	0	368	0	0
T133	0	4	0	0
T134	0	25	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12498756	5481	0	0
T8	79609	46	0	0
T9	10739	25	0	0
T10	1608	0	0	0
T11	1587	0	0	0
T12	2422	0	0	0
T13	3775	0	0	0
T14	31322	0	0	0
T15	2217	0	0	0
T25	3571	0	0	0
T26	2673	0	0	0
T51	0	57	0	0
T65	0	31	0	0
T88	0	289	0	0
T89	0	1	0	0
T92	0	4	0	0
T101	0	91	0	0
T133	0	2	0	0
T134	0	37	0	0