Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	640571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

387399

1

T1

128

T2

1

T3

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	549857	1			T1	186		T3	63		T4	3970
values[0x0]	238381	1			T1	101		T2	3		T3	35
values[0x1]	239732	1			T1	92		T2	3		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	537223	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

490747

1

T1

164

T2

2

T3

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3350	1			T4	14		T5	3		T9	2
valid_sources[0x01]	3617	1			T1	1		T3	1		T4	34
valid_sources[0x02]	5377	1			T1	4		T3	1		T4	27
valid_sources[0x03]	3497	1			T1	1		T4	17		T5	1
valid_sources[0x04]	6593	1			T1	2		T4	37		T5	3
valid_sources[0x05]	3925	1			T1	3		T3	2		T4	36
valid_sources[0x06]	3736	1			T1	2		T4	19		T11	10
valid_sources[0x07]	3305	1			T1	1		T4	32		T9	2
valid_sources[0x08]	4046	1			T3	2		T4	26		T5	13
valid_sources[0x09]	4114	1			T3	2		T4	25		T11	10
valid_sources[0x0a]	3836	1			T4	19		T5	1		T9	1
valid_sources[0x0b]	3705	1			T1	4		T4	20		T5	4
valid_sources[0x0c]	3499	1			T1	2		T4	28		T5	5
valid_sources[0x0d]	7603	1			T1	4		T4	28		T5	5
valid_sources[0x0e]	3501	1			T1	4		T4	29		T5	7
valid_sources[0x0f]	3579	1			T1	1		T4	38		T5	5
valid_sources[0x10]	4132	1			T4	24		T5	3		T9	1
valid_sources[0x11]	3406	1			T1	1		T4	20		T11	15
valid_sources[0x12]	7426	1			T1	1		T3	1		T4	27
valid_sources[0x13]	3856	1			T1	1		T4	36		T11	14
valid_sources[0x14]	3370	1			T1	1		T3	1		T4	25
valid_sources[0x15]	4070	1			T1	1		T3	3		T4	32
valid_sources[0x16]	5518	1			T1	2		T3	1		T4	29
valid_sources[0x17]	3134	1			T1	1		T4	19		T5	1
valid_sources[0x18]	4529	1			T3	2		T4	21		T5	1
valid_sources[0x19]	3507	1			T4	22		T5	2		T11	8
valid_sources[0x1a]	3808	1			T4	33		T11	5		T15	2
valid_sources[0x1b]	3745	1			T3	3		T4	21		T5	5
valid_sources[0x1c]	3948	1			T3	1		T4	22		T5	2
valid_sources[0x1d]	4364	1			T1	2		T3	1		T4	19
valid_sources[0x1e]	4312	1			T1	1		T4	29		T5	1
valid_sources[0x1f]	4119	1			T1	2		T4	23		T5	1
valid_sources[0x20]	3698	1			T1	1		T3	1		T4	23
valid_sources[0x21]	3644	1			T1	1		T4	33		T5	5
valid_sources[0x22]	4590	1			T1	7		T4	26		T5	3
valid_sources[0x23]	6352	1			T1	5		T4	37		T5	2
valid_sources[0x24]	3471	1			T1	2		T3	1		T4	23
valid_sources[0x25]	3849	1			T4	37		T5	1		T11	8
valid_sources[0x26]	7126	1			T1	2		T4	33		T5	1
valid_sources[0x27]	3977	1			T1	7		T3	1		T4	30
valid_sources[0x28]	3805	1			T1	2		T3	1		T4	21
valid_sources[0x29]	3301	1			T1	1		T4	20		T5	1
valid_sources[0x2a]	3816	1			T1	2		T4	34		T11	20
valid_sources[0x2b]	3450	1			T3	1		T4	26		T5	1
valid_sources[0x2c]	3799	1			T1	3		T3	1		T4	40
valid_sources[0x2d]	3231	1			T1	2		T4	26		T11	19
valid_sources[0x2e]	3210	1			T2	4		T3	2		T4	22
valid_sources[0x2f]	3800	1			T1	1		T4	26		T5	1
valid_sources[0x30]	3552	1			T1	3		T4	31		T11	15
valid_sources[0x31]	3811	1			T1	2		T4	34		T5	2
valid_sources[0x32]	4505	1			T4	34		T11	6		T13	78
valid_sources[0x33]	3999	1			T1	3		T4	21		T11	5
valid_sources[0x34]	4382	1			T1	3		T3	1		T4	26
valid_sources[0x35]	3508	1			T4	34		T5	1		T11	12
valid_sources[0x36]	3102	1			T1	1		T3	1		T4	37
valid_sources[0x37]	4012	1			T1	3		T4	40		T9	2
valid_sources[0x38]	3120	1			T1	2		T3	3		T4	21
valid_sources[0x39]	3890	1			T1	1		T4	23		T9	1
valid_sources[0x3a]	3760	1			T1	4		T4	27		T5	1
valid_sources[0x3b]	3546	1			T1	1		T4	43		T9	1
valid_sources[0x3c]	3792	1			T1	1		T4	27		T9	1
valid_sources[0x3d]	3584	1			T4	16		T9	1		T11	7
valid_sources[0x3e]	3880	1			T1	2		T3	1		T4	22
valid_sources[0x3f]	4086	1			T1	1		T3	2		T4	23
valid_sources[0x40]	3299	1			T3	2		T4	36		T11	13
valid_sources[0x41]	4022	1			T3	2		T4	22		T5	5
valid_sources[0x42]	3652	1			T1	1		T4	26		T9	2
valid_sources[0x43]	3366	1			T1	2		T3	1		T4	26
valid_sources[0x44]	4533	1			T1	2		T3	1		T4	46
valid_sources[0x45]	7025	1			T1	1		T3	2		T4	43
valid_sources[0x46]	4518	1			T1	2		T3	1		T4	16
valid_sources[0x47]	3296	1			T1	1		T4	42		T8	1
valid_sources[0x48]	4196	1			T1	1		T4	23		T5	1
valid_sources[0x49]	3366	1			T1	2		T4	36		T5	2
valid_sources[0x4a]	4010	1			T3	1		T4	12		T5	2
valid_sources[0x4b]	3867	1			T1	2		T4	46		T5	1
valid_sources[0x4c]	3713	1			T1	1		T4	25		T9	1
valid_sources[0x4d]	3825	1			T1	1		T4	33		T5	2
valid_sources[0x4e]	3618	1			T3	1		T4	29		T5	2
valid_sources[0x4f]	4467	1			T4	30		T5	1		T9	2
valid_sources[0x50]	3819	1			T1	1		T4	21		T5	2
valid_sources[0x51]	4138	1			T1	1		T4	20		T11	8
valid_sources[0x52]	3483	1			T1	1		T3	1		T4	44
valid_sources[0x53]	3760	1			T1	1		T4	22		T5	1
valid_sources[0x54]	3772	1			T1	2		T4	48		T5	2
valid_sources[0x55]	4059	1			T4	31		T5	2		T9	1
valid_sources[0x56]	3505	1			T1	3		T4	36		T5	4
valid_sources[0x57]	3805	1			T4	42		T5	2		T9	2
valid_sources[0x58]	5314	1			T1	1		T4	21		T5	4
valid_sources[0x59]	4606	1			T4	33		T5	1		T9	1
valid_sources[0x5a]	3621	1			T4	23		T9	2		T11	19
valid_sources[0x5b]	3512	1			T1	1		T3	1		T4	26
valid_sources[0x5c]	7299	1			T1	1		T4	29		T5	1
valid_sources[0x5d]	3670	1			T4	21		T5	1		T9	1
valid_sources[0x5e]	4533	1			T1	3		T4	35		T5	1
valid_sources[0x5f]	3259	1			T1	1		T3	1		T4	18
valid_sources[0x60]	3559	1			T3	1		T4	27		T5	3
valid_sources[0x61]	3226	1			T1	2		T3	1		T4	18
valid_sources[0x62]	3351	1			T1	3		T4	36		T5	4
valid_sources[0x63]	3694	1			T1	1		T4	21		T5	1
valid_sources[0x64]	3879	1			T1	5		T2	1		T4	24
valid_sources[0x65]	4506	1			T1	1		T4	38		T11	13
valid_sources[0x66]	4281	1			T1	3		T3	1		T4	20
valid_sources[0x67]	3082	1			T1	2		T4	29		T11	8
valid_sources[0x68]	3684	1			T1	3		T3	1		T4	23
valid_sources[0x69]	3423	1			T4	32		T5	2		T9	1
valid_sources[0x6a]	3598	1			T3	1		T4	32		T5	1
valid_sources[0x6b]	3159	1			T3	1		T4	23		T5	1
valid_sources[0x6c]	3752	1			T1	2		T3	1		T4	30
valid_sources[0x6d]	3668	1			T4	32		T5	1		T9	2
valid_sources[0x6e]	5165	1			T1	1		T3	2		T4	39
valid_sources[0x6f]	4043	1			T1	1		T4	37		T5	1
valid_sources[0x70]	4385	1			T3	3		T4	30		T5	1
valid_sources[0x71]	3370	1			T1	3		T3	1		T4	34
valid_sources[0x72]	3430	1			T1	3		T4	30		T5	1
valid_sources[0x73]	3705	1			T1	2		T3	2		T4	14
valid_sources[0x74]	4488	1			T1	5		T3	1		T4	25
valid_sources[0x75]	4728	1			T1	3		T4	13		T5	3
valid_sources[0x76]	6993	1			T1	3		T4	45		T5	2
valid_sources[0x77]	2922	1			T1	1		T3	1		T4	37
valid_sources[0x78]	4079	1			T1	1		T4	26		T9	1
valid_sources[0x79]	3191	1			T1	2		T4	19		T5	3
valid_sources[0x7a]	4696	1			T4	36		T5	3		T9	2
valid_sources[0x7b]	3098	1			T4	32		T5	1		T9	1
valid_sources[0x7c]	4614	1			T4	10		T5	1		T11	16
valid_sources[0x7d]	3330	1			T1	4		T3	1		T4	32
valid_sources[0x7e]	3768	1			T1	2		T4	21		T5	2
valid_sources[0x7f]	4128	1			T1	1		T4	23		T5	2
valid_sources[0x80]	3880	1			T1	2		T3	1		T4	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

258878

1

T1

84

T3

35

T4

1869

values[0x0]

all_enables

biggest_size

83642

1

T1

32

T2

1

T3

6

values[0x1]

all_enables

biggest_size

44879

1

T1

12

T3

5

T4

252