Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T4,T5

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57428602	9224	0	0
CascadeEffAonToRstPorAboveRise_A	57428602	9224	0	0
CascadeEffAonToRstPorIoAboveFall_A	55129642	9224	0	0
CascadeEffAonToRstPorIoAboveRise_A	55129642	9224	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27565548	9224	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27565548	9224	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13782487	9224	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13782487	9224	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27565759	9224	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27565759	9224	0	0
CascadeLcToLcAboveFall_A	57428602	22768	0	0
CascadeLcToLcAboveRise_A	57428602	22768	0	0
CascadeLcToLcAonAboveFall_A	1740544	22768	0	0
CascadeLcToLcAonAboveRise_A	1740544	22768	0	0
CascadeLcToLcShadowedAboveFall_A	57428602	22768	0	0
CascadeLcToLcShadowedAboveRise_A	57428602	22768	0	0
CascadePorToAonAboveFall_A	1740544	7261	0	0
CascadeSysToSysAboveFall_A	57428602	22768	0	0
CascadeSysToSysAboveRise_A	57428602	22768	0	0
ScanRstToAonRise_A	1740544	233	0	0
StablePorToAonRise_A	1740544	9224	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12208778	22768	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12208778	22768	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12208778	22768	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12208778	22768	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13782487	22768	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13782487	22768	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12208778	22768	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12208778	22768	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12208778	22768	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12208778	22768	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	9224	0	0
T1	19254	2	0	0
T2	5856	1	0	0
T3	9310	1	0	0
T4	381851	49	0	0
T5	20018	2	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	2	0	0
T10	24411	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	9224	0	0
T1	19254	2	0	0
T2	5856	1	0	0
T3	9310	1	0	0
T4	381851	49	0	0
T5	20018	2	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	2	0	0
T10	24411	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55129642	9224	0	0
T1	18491	2	0	0
T2	5621	1	0	0
T3	8938	1	0	0
T4	366559	49	0	0
T5	19217	2	0	0
T6	23375	8	0	0
T7	23311	8	0	0
T8	795908	271	0	0
T9	9857	2	0	0
T10	23420	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55129642	9224	0	0
T1	18491	2	0	0
T2	5621	1	0	0
T3	8938	1	0	0
T4	366559	49	0	0
T5	19217	2	0	0
T6	23375	8	0	0
T7	23311	8	0	0
T8	795908	271	0	0
T9	9857	2	0	0
T10	23420	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565548	9224	0	0
T1	9245	2	0	0
T2	2810	1	0	0
T3	4469	1	0	0
T4	183293	49	0	0
T5	9608	2	0	0
T6	11691	8	0	0
T7	11657	8	0	0
T8	397916	271	0	0
T9	4928	2	0	0
T10	11715	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565548	9224	0	0
T1	9245	2	0	0
T2	2810	1	0	0
T3	4469	1	0	0
T4	183293	49	0	0
T5	9608	2	0	0
T6	11691	8	0	0
T7	11657	8	0	0
T8	397916	271	0	0
T9	4928	2	0	0
T10	11715	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	9224	0	0
T1	4622	2	0	0
T2	1403	1	0	0
T3	2234	1	0	0
T4	91654	49	0	0
T5	4804	2	0	0
T6	5846	8	0	0
T7	5827	8	0	0
T8	198946	271	0	0
T9	2462	2	0	0
T10	5854	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	9224	0	0
T1	4622	2	0	0
T2	1403	1	0	0
T3	2234	1	0	0
T4	91654	49	0	0
T5	4804	2	0	0
T6	5846	8	0	0
T7	5827	8	0	0
T8	198946	271	0	0
T9	2462	2	0	0
T10	5854	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565759	9224	0	0
T1	9241	2	0	0
T2	2811	1	0	0
T3	4469	1	0	0
T4	183273	49	0	0
T5	9608	2	0	0
T6	11689	8	0	0
T7	11658	8	0	0
T8	397941	271	0	0
T9	4927	2	0	0
T10	11718	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565759	9224	0	0
T1	9241	2	0	0
T2	2811	1	0	0
T3	4469	1	0	0
T4	183273	49	0	0
T5	9608	2	0	0
T6	11689	8	0	0
T7	11658	8	0	0
T8	397941	271	0	0
T9	4927	2	0	0
T10	11718	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	22768	0	0
T1	19254	6	0	0
T2	5856	1	0	0
T3	9310	7	0	0
T4	381851	127	0	0
T5	20018	6	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	6	0	0
T10	24411	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	22768	0	0
T1	19254	6	0	0
T2	5856	1	0	0
T3	9310	7	0	0
T4	381851	127	0	0
T5	20018	6	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	6	0	0
T10	24411	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	22768	0	0
T1	576	6	0	0
T2	174	1	0	0
T3	277	7	0	0
T4	11605	127	0	0
T5	599	6	0	0
T6	733	8	0	0
T7	730	8	0	0
T8	24992	271	0	0
T9	306	6	0	0
T10	733	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	22768	0	0
T1	576	6	0	0
T2	174	1	0	0
T3	277	7	0	0
T4	11605	127	0	0
T5	599	6	0	0
T6	733	8	0	0
T7	730	8	0	0
T8	24992	271	0	0
T9	306	6	0	0
T10	733	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	22768	0	0
T1	19254	6	0	0
T2	5856	1	0	0
T3	9310	7	0	0
T4	381851	127	0	0
T5	20018	6	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	6	0	0
T10	24411	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	22768	0	0
T1	19254	6	0	0
T2	5856	1	0	0
T3	9310	7	0	0
T4	381851	127	0	0
T5	20018	6	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	6	0	0
T10	24411	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	7261	0	0
T1	576	1	0	0
T2	174	1	0	0
T3	277	1	0	0
T4	11605	28	0	0
T5	599	1	0	0
T6	733	8	0	0
T7	730	8	0	0
T8	24992	271	0	0
T9	306	1	0	0
T10	733	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	22768	0	0
T1	19254	6	0	0
T2	5856	1	0	0
T3	9310	7	0	0
T4	381851	127	0	0
T5	20018	6	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	6	0	0
T10	24411	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57428602	22768	0	0
T1	19254	6	0	0
T2	5856	1	0	0
T3	9310	7	0	0
T4	381851	127	0	0
T5	20018	6	0	0
T6	24361	8	0	0
T7	24270	8	0	0
T8	828952	271	0	0
T9	10266	6	0	0
T10	24411	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	233	0	0
T4	11605	1	0	0
T5	599	0	0	0
T6	733	0	0	0
T7	730	0	0	0
T8	24992	0	0	0
T9	306	0	0	0
T10	733	0	0	0
T11	6128	2	0	0
T12	364	0	0	0
T16	0	4	0	0
T28	0	1	0	0
T47	0	5	0	0
T58	315	0	0	0
T66	0	1	0	0
T95	0	2	0	0
T97	0	4	0	0
T132	0	1	0	0
T133	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	9224	0	0
T1	576	2	0	0
T2	174	1	0	0
T3	277	1	0	0
T4	11605	49	0	0
T5	599	2	0	0
T6	733	8	0	0
T7	730	8	0	0
T8	24992	271	0	0
T9	306	2	0	0
T10	733	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	22768	0	0
T1	4622	6	0	0
T2	1403	1	0	0
T3	2234	7	0	0
T4	91654	127	0	0
T5	4804	6	0	0
T6	5846	8	0	0
T7	5827	8	0	0
T8	198946	271	0	0
T9	2462	6	0	0
T10	5854	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	22768	0	0
T1	4622	6	0	0
T2	1403	1	0	0
T3	2234	7	0	0
T4	91654	127	0	0
T5	4804	6	0	0
T6	5846	8	0	0
T7	5827	8	0	0
T8	198946	271	0	0
T9	2462	6	0	0
T10	5854	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12208778	22768	0	0
T1	4380	6	0	0
T2	1386	1	0	0
T3	1753	7	0	0
T4	81173	127	0	0
T5	4562	6	0	0
T6	5491	8	0	0
T7	5089	8	0	0
T8	180442	271	0	0
T9	2222	6	0	0
T10	5504	8	0	0