Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T13
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T13,T16
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13782487	14489	0	0
gen_assertions[0].RstEnOn_A	13782487	1151	0	0
gen_assertions[0].RstNOff_A	13782487	14489	0	0
gen_assertions[0].RstNOn_A	13782487	1151	0	0
gen_assertions[1].RstEnOff_A	55129642	13175	0	0
gen_assertions[1].RstEnOn_A	55129642	1088	0	0
gen_assertions[1].RstNOff_A	55129642	13175	0	0
gen_assertions[1].RstNOn_A	55129642	1088	0	0
gen_assertions[2].RstEnOff_A	27565548	13210	0	0
gen_assertions[2].RstEnOn_A	27565548	1064	0	0
gen_assertions[2].RstNOff_A	27565548	13210	0	0
gen_assertions[2].RstNOn_A	27565548	1064	0	0
gen_assertions[3].RstEnOff_A	27565759	13273	0	0
gen_assertions[3].RstEnOn_A	27565759	1117	0	0
gen_assertions[3].RstNOff_A	27565759	13273	0	0
gen_assertions[3].RstNOn_A	27565759	1117	0	0
gen_assertions[4].RstEnOff_A	1740544	22681	0	0
gen_assertions[4].RstEnOn_A	1740544	1187	0	0
gen_assertions[4].RstNOff_A	1740544	22681	0	0
gen_assertions[4].RstNOn_A	1740544	1187	0	0
gen_assertions[5].RstEnOff_A	13782487	14717	0	0
gen_assertions[5].RstEnOn_A	13782487	1212	0	0
gen_assertions[5].RstNOff_A	13782487	14717	0	0
gen_assertions[5].RstNOn_A	13782487	1212	0	0
gen_assertions[6].RstEnOff_A	13782487	14776	0	0
gen_assertions[6].RstEnOn_A	13782487	1274	0	0
gen_assertions[6].RstNOff_A	13782487	14776	0	0
gen_assertions[6].RstNOn_A	13782487	1274	0	0
gen_assertions[7].RstEnOff_A	13782487	14847	0	0
gen_assertions[7].RstEnOn_A	13782487	1352	0	0
gen_assertions[7].RstNOff_A	13782487	14847	0	0
gen_assertions[7].RstNOn_A	13782487	1352	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14489	0	0
T1	4622	4	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	89	0	0
T5	4804	4	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1151	0	0
T3	2234	4	0	0
T4	91654	12	0	0
T5	4804	0	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T11	48452	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T16	0	7	0	0
T27	0	5	0	0
T29	0	1	0	0
T31	0	3	0	0
T52	0	6	0	0
T54	0	2	0	0
T58	2536	0	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14489	0	0
T1	4622	4	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	89	0	0
T5	4804	4	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1151	0	0
T3	2234	4	0	0
T4	91654	12	0	0
T5	4804	0	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T11	48452	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T16	0	7	0	0
T27	0	5	0	0
T29	0	1	0	0
T31	0	3	0	0
T52	0	6	0	0
T54	0	2	0	0
T58	2536	0	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55129642	13175	0	0
T1	18491	4	0	0
T2	5621	0	0	0
T3	8938	6	0	0
T4	366559	87	0	0
T5	19217	5	0	0
T6	23375	0	0	0
T7	23311	0	0	0
T8	795908	0	0	0
T9	9857	3	0	0
T10	23420	0	0	0
T11	0	31	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	7	0	0
T15	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55129642	1088	0	0
T3	8938	4	0	0
T4	366559	15	0	0
T5	19217	1	0	0
T6	23375	0	0	0
T7	23311	0	0	0
T8	795908	0	0	0
T9	9857	0	0	0
T10	23420	0	0	0
T11	193815	0	0	0
T13	0	4	0	0
T16	0	9	0	0
T27	0	6	0	0
T31	0	4	0	0
T52	0	4	0	0
T54	0	2	0	0
T58	10148	0	0	0
T80	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55129642	13175	0	0
T1	18491	4	0	0
T2	5621	0	0	0
T3	8938	6	0	0
T4	366559	87	0	0
T5	19217	5	0	0
T6	23375	0	0	0
T7	23311	0	0	0
T8	795908	0	0	0
T9	9857	3	0	0
T10	23420	0	0	0
T11	0	31	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	7	0	0
T15	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55129642	1088	0	0
T3	8938	4	0	0
T4	366559	15	0	0
T5	19217	1	0	0
T6	23375	0	0	0
T7	23311	0	0	0
T8	795908	0	0	0
T9	9857	0	0	0
T10	23420	0	0	0
T11	193815	0	0	0
T13	0	4	0	0
T16	0	9	0	0
T27	0	6	0	0
T31	0	4	0	0
T52	0	4	0	0
T54	0	2	0	0
T58	10148	0	0	0
T80	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565548	13210	0	0
T1	9245	4	0	0
T2	2810	0	0	0
T3	4469	6	0	0
T4	183293	87	0	0
T5	9608	5	0	0
T6	11691	0	0	0
T7	11657	0	0	0
T8	397916	0	0	0
T9	4928	3	0	0
T10	11715	0	0	0
T11	0	31	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565548	1064	0	0
T3	4469	1	0	0
T4	183293	14	0	0
T5	9608	1	0	0
T6	11691	0	0	0
T7	11657	0	0	0
T8	397916	0	0	0
T9	4928	0	0	0
T10	11715	0	0	0
T11	96914	0	0	0
T13	0	3	0	0
T16	0	5	0	0
T27	0	6	0	0
T31	0	3	0	0
T52	0	5	0	0
T54	0	4	0	0
T58	5074	0	0	0
T80	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565548	13210	0	0
T1	9245	4	0	0
T2	2810	0	0	0
T3	4469	6	0	0
T4	183293	87	0	0
T5	9608	5	0	0
T6	11691	0	0	0
T7	11657	0	0	0
T8	397916	0	0	0
T9	4928	3	0	0
T10	11715	0	0	0
T11	0	31	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565548	1064	0	0
T3	4469	1	0	0
T4	183293	14	0	0
T5	9608	1	0	0
T6	11691	0	0	0
T7	11657	0	0	0
T8	397916	0	0	0
T9	4928	0	0	0
T10	11715	0	0	0
T11	96914	0	0	0
T13	0	3	0	0
T16	0	5	0	0
T27	0	6	0	0
T31	0	3	0	0
T52	0	5	0	0
T54	0	4	0	0
T58	5074	0	0	0
T80	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565759	13273	0	0
T1	9241	4	0	0
T2	2811	0	0	0
T3	4469	6	0	0
T4	183273	87	0	0
T5	9608	5	0	0
T6	11689	0	0	0
T7	11658	0	0	0
T8	397941	0	0	0
T9	4927	3	0	0
T10	11718	0	0	0
T11	0	31	0	0
T12	0	4	0	0
T13	0	6	0	0
T14	0	7	0	0
T15	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565759	1117	0	0
T4	183273	15	0	0
T5	9608	1	0	0
T6	11689	0	0	0
T7	11658	0	0	0
T8	397941	0	0	0
T9	4927	0	0	0
T10	11718	0	0	0
T11	96918	0	0	0
T12	5847	0	0	0
T13	0	6	0	0
T16	0	5	0	0
T27	0	7	0	0
T31	0	6	0	0
T52	0	8	0	0
T54	0	5	0	0
T58	5073	0	0	0
T62	0	10	0	0
T80	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565759	13273	0	0
T1	9241	4	0	0
T2	2811	0	0	0
T3	4469	6	0	0
T4	183273	87	0	0
T5	9608	5	0	0
T6	11689	0	0	0
T7	11658	0	0	0
T8	397941	0	0	0
T9	4927	3	0	0
T10	11718	0	0	0
T11	0	31	0	0
T12	0	4	0	0
T13	0	6	0	0
T14	0	7	0	0
T15	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27565759	1117	0	0
T4	183273	15	0	0
T5	9608	1	0	0
T6	11689	0	0	0
T7	11658	0	0	0
T8	397941	0	0	0
T9	4927	0	0	0
T10	11718	0	0	0
T11	96918	0	0	0
T12	5847	0	0	0
T13	0	6	0	0
T16	0	5	0	0
T27	0	7	0	0
T31	0	6	0	0
T52	0	8	0	0
T54	0	5	0	0
T58	5073	0	0	0
T62	0	10	0	0
T80	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	22681	0	0
T1	576	6	0	0
T2	174	1	0	0
T3	277	6	0	0
T4	11605	138	0	0
T5	599	6	0	0
T6	733	3	0	0
T7	730	2	0	0
T8	24992	271	0	0
T9	306	5	0	0
T10	733	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	1187	0	0
T4	11605	12	0	0
T5	599	0	0	0
T6	733	0	0	0
T7	730	0	0	0
T8	24992	0	0	0
T9	306	0	0	0
T10	733	0	0	0
T11	6128	0	0	0
T12	364	0	0	0
T13	0	8	0	0
T16	0	8	0	0
T27	0	10	0	0
T31	0	5	0	0
T52	0	10	0	0
T54	0	5	0	0
T58	315	0	0	0
T80	0	8	0	0
T81	0	1	0	0
T82	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	22681	0	0
T1	576	6	0	0
T2	174	1	0	0
T3	277	6	0	0
T4	11605	138	0	0
T5	599	6	0	0
T6	733	3	0	0
T7	730	2	0	0
T8	24992	271	0	0
T9	306	5	0	0
T10	733	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1740544	1187	0	0
T4	11605	12	0	0
T5	599	0	0	0
T6	733	0	0	0
T7	730	0	0	0
T8	24992	0	0	0
T9	306	0	0	0
T10	733	0	0	0
T11	6128	0	0	0
T12	364	0	0	0
T13	0	8	0	0
T16	0	8	0	0
T27	0	10	0	0
T31	0	5	0	0
T52	0	10	0	0
T54	0	5	0	0
T58	315	0	0	0
T80	0	8	0	0
T81	0	1	0	0
T82	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14717	0	0
T1	4622	4	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	93	0	0
T5	4804	4	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	5	0	0
T13	0	7	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1212	0	0
T4	91654	16	0	0
T5	4804	0	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T11	48452	0	0	0
T12	2924	1	0	0
T13	0	7	0	0
T16	0	6	0	0
T27	0	11	0	0
T31	0	7	0	0
T52	0	13	0	0
T54	0	7	0	0
T58	2536	0	0	0
T62	0	12	0	0
T80	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14717	0	0
T1	4622	4	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	93	0	0
T5	4804	4	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	5	0	0
T13	0	7	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1212	0	0
T4	91654	16	0	0
T5	4804	0	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T11	48452	0	0	0
T12	2924	1	0	0
T13	0	7	0	0
T16	0	6	0	0
T27	0	11	0	0
T31	0	7	0	0
T52	0	13	0	0
T54	0	7	0	0
T58	2536	0	0	0
T62	0	12	0	0
T80	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14776	0	0
T1	4622	5	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	90	0	0
T5	4804	4	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	4	0	0
T13	0	9	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1274	0	0
T1	4622	1	0	0
T2	1403	0	0	0
T3	2234	0	0	0
T4	91654	13	0	0
T5	4804	0	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T13	0	9	0	0
T16	0	7	0	0
T27	0	12	0	0
T31	0	8	0	0
T52	0	13	0	0
T54	0	8	0	0
T62	0	11	0	0
T80	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14776	0	0
T1	4622	5	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	90	0	0
T5	4804	4	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	4	0	0
T13	0	9	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1274	0	0
T1	4622	1	0	0
T2	1403	0	0	0
T3	2234	0	0	0
T4	91654	13	0	0
T5	4804	0	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T13	0	9	0	0
T16	0	7	0	0
T27	0	12	0	0
T31	0	8	0	0
T52	0	13	0	0
T54	0	8	0	0
T62	0	11	0	0
T80	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14847	0	0
T1	4622	4	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	90	0	0
T5	4804	5	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	4	0	0
T13	0	11	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1352	0	0
T4	91654	13	0	0
T5	4804	1	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T11	48452	0	0	0
T12	2924	0	0	0
T13	0	11	0	0
T16	0	7	0	0
T27	0	14	0	0
T31	0	10	0	0
T52	0	11	0	0
T54	0	8	0	0
T58	2536	0	0	0
T62	0	15	0	0
T80	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	14847	0	0
T1	4622	4	0	0
T2	1403	0	0	0
T3	2234	6	0	0
T4	91654	90	0	0
T5	4804	5	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	4	0	0
T10	5854	0	0	0
T11	0	36	0	0
T12	0	4	0	0
T13	0	11	0	0
T14	0	7	0	0
T15	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13782487	1352	0	0
T4	91654	13	0	0
T5	4804	1	0	0
T6	5846	0	0	0
T7	5827	0	0	0
T8	198946	0	0	0
T9	2462	0	0	0
T10	5854	0	0	0
T11	48452	0	0	0
T12	2924	0	0	0
T13	0	11	0	0
T16	0	7	0	0
T27	0	14	0	0
T31	0	10	0	0
T52	0	11	0	0
T54	0	8	0	0
T58	2536	0	0	0
T62	0	15	0	0
T80	0	12	0	0